Signal Integrity

The resources on this page are designed to give you everything you need to achieve reliable system-level designs with AMD adaptive SoCs and FPGAs on the first try.

AMD provides an extensive collection of documentation and tools for simulation. We support signal integrity simulation models and design kits:

• IBIS/IBIS-AMI models and power delivery network models  

• Versal™ and UltraScale™ architecture transceiver SI and PI simulation kits

• UltraScale+™ architecture DDR4 simulation kits and DDRx timing models

• Versal architecture DDR4 and LPDDR4 timing models 

Feature size reduction and the need for reduced power consumption have driven core voltages down from the old standard of 3.3V to the 0.9V range. This change in voltage and signal frequency content requires us to use new design practices that take into account electrical effects that could previously be ignored.

• PCB Design Considerations for FPGA Accelerator Cards (PDF)
  An overview of PCB design challenges, including dielectric material selection, PCB fabrication technologies, and layout best practices for high-speed memory design, SerDes channel design, and power delivery network design.

• Signal Integrity and High-speed PCB Design: Issues, Tools, and Methodologies (PDF)
  This series of articles explores tools and methods you can use to combat signal and power integrity distortions throughout product development.

The AMD Versal and UltraScale architecture transceiver portfolio covers the gamut of today’s high-speed interconnects and delivers exceptional value:

• Versal Adaptive SoC GTM Transceivers Architecture Manual

• Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual

• IEEE Education Session - Overview of ADC-based Wireline Transceiver

• DesignCon Tutorial on PAM4 Signaling 

The following white papers demonstrate how to use multiple EDA tools with AMD models (such as Keysight ADS) to perform signal and power integrity simulations.

Power Integrity

• Simulating FPGA Power Integrity Using S-Parameter Models

High-speed Serial Transceivers

• SerDes Channel Simulation in FPGAs Using IBIS-AMI
• Equalization for High-Speed Serial Interfaces in AMD 7 Series FPGA Transceivers
• PCB Channel Design Guidelines for Versal Adaptive SoC GTM Transceivers 

PCB Design

• 7 Series FPGAs PCB Design Guide

• UltraScale Architecture PCB Design User Guide

• Versal Adaptive SoC PCB Design User Guide  

When designing a board with elaborate ICs, such as with adaptive SoCs and FPGAs, it is important to calculate the device demand on the PCB and vice-versa. Below you will find information on signal integrity, static and dynamic power, and SSO:

• Managing Simultaneously Switching Output (SSO) Noise
• Power Calculators and Estimators
  

Analyze and design power and return current paths with information on bypass capacitor selection, power consumption, and voltage regulators.

• Learn more about power supplies and power distribution systems

AMD offers high-density package routing information, a detailed PCB design checklist, and many other resources to ensure that you consider all the issues when designing a PCB.

• Versal Schematic Checker Tool 

• Review DVD Reference Material (PDF)
• AMD Adaptive Computing Customer Training Center