Xilinx 7nm Versal device IP portfolio will be published in Q2, 2019. Please stay tuned.

Xilinx 16nm UltraScale+ devices integrate many essential PCI Express features required for today’s Data center, Communications and embedded applications.  UltraScale+ devices use two types of integrated blocks: PCIE4 and PCIE4C, with most devices using the PCIE4 blocks.

The PCIE4 blocks are compliant to PCI Express Base Specification v3.1 and support up to Gen3 x16, and can also be configured for lower link width and speeds. The PCIE4 block does not support Gen4 operation.

PCIE4C blocks are compliant to the PCI Express Base Specification v3.1 supporting up to 8.0GT/s (Gen3) and compatible with PCI Express Base Specification v4.0 supporting up to 16.0GT/s (Gen4). PCIE4C blocks are also compliant with CCIX Base Specification v1.0 Version 0.9, supporting speeds up to 16.0GT/s.  PCIE4C blocks support up to 16 lanes at Gen3 or up to 8 lanes at Gen4 and can be configured for lower link widths and speeds to conserve resources and power.

Some devices, such as Virtex UltraScale+ HBM FPGAs, have only PCIE4C blocks or a combination of both PCIE4 and PCIE4C blocks. The PCIE4C block can implement both PCI Express and CCIX while PCIE4 blocks can implement only PCI Express.

All integrated blocks for PCIe in the UltraScale architecture can be configured as Endpoint or Root Port.  The Root Port can be used to build the basis for a compatible Root Complex, to allow custom chip-to-chip communication via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet Controllers or Fibre Channel HBAs or NVMe SSDs, to the FPGA, MPSoC, or RFSoC.

The Integrated Block for PCI Express IP is hardened in silicon, and supports:

• Native Gen3x16 Integrated PCIe block for 100G applications.  For specific link widths and speeds that are supported, see the appropriate Product Guide for the desired IP (PG213, PG195, PG302 or PG239)
• Gen4 x8 PCIe inter-operability is supported on a limited set of devices – VU31P, VU33P, VU35P and VU37P. Note that these limited number of devices are compatible with the PCI Express Base Specification Revision 4.0, Version 1.0.  For details about limitations see Product Guide PG213.
• Supports 4 Physical and 252 Virtual Functions required for Single Root IO Virtualization (SR-IOV) to share IO resources
• Larger number of tags (256) to support more PCIe requests enabling overall system performance
• Integrated MSI-X tables
• See Product Guide PG213 for further details

Xilinx also offers high performance DMA and Bridge solutions as soft IP:

• Xilinx XDMA IP sub-system (Product Page for XDMA) is our production PCIe DMA solution, widely used by customers. The XDMA also provides AXI PCIe Bridge functionality.  See Product Guide PG195 for more details.
• Xilinx QDMA IP sub-system (Product Page for QDMA) is our new DMA IP, available for production in Vivado 2018.3.  The QDMA solution provides support for multiple Physical/Virtual Functions with scalable queues, and is ideal for applications that require small packet performance at low latency. The QDMA also provides AXI PCIe Bridge functionality.  See Product Guide PG302

Xilinx provides a hardened PHY IP block. See Product Guide PG239 for details.  Partners Northwest Logic and PLDA provides soft PCIe Cores that work with the Xilinx PHY.

Xilinx 20nm UltraScale+ devices integrate many essential PCI Express features required for today’s Data center, Communications and embedded applications.

The Integrated Block for PCI Express IP is hardened in silicon, and supports:

• Native Gen3 x8 Integrated PCIe block for 100G applications.  For specific link widths and speeds that are supported, see the appropriate Product Guide for the desired IP (PG054, PG055 or PG195)
  
• Supports 64 tags for PCIe requests
• Multi-Vector MSI for up to 32 vectors and MSI-X
• See Product Guide PG156 for further details

Xilinx also offers high performance DMA and Bridge solutions as soft IP:

• Xilinx XDMA IP sub-system (Product Page for XDMA) is our production PCIe DMA solution, widely used by customers.  See Product Guide PG195 for more details.
• Xilinx AXI Bridge for PCIe Express is a production IP. See Product Guide PG194 for further details.

*For specific link widths and speeds that are supported, see the appropriate Product Guide for the desired IP (PG156, PG195 or PG239)

Xilinx provides a hardened PHY block. See Product Guide PG239 for details.  Partners Northwest Logic and PLDA provides soft PCIe Cores that work with the Xilinx PHY.

Xilinx 28nm 7-Series devices integrate many essential PCI Express features required for today’s Data center, Communications and embedded applications.

The Integrated Block for PCI Express IP is hardened in silicon, and supports:

• Native Gen3 x8* Integrated PCIe block
• Supports 64-bit and 128bit data widths
• See Product Guide PG054 for further details

Xilinx also offers high performance DMA and Bridge solutions as soft IP:

• Xilinx XDMA IP sub-system (Product Page for XDMA) is our production PCIe DMA solution, widely used by customers.  See Product Guide PG195 for more information.
• Xilinx provides a production AXI Memory Mapped to PCI Express Gen2 IP. See (Product Guide PG055) for further details.

*For specific link widths and speeds that are supported, see the appropriate Product Guide for the desired IP (PG054, PG055 or PG195)