SmartRAM

Build the right memory for any application. The Virtex™-4 Smart RAM hierarchy enables you to achieve compact utilization and highest performance.

Shift Register SRL16 block

• Configure any CLB Look-Up Table (LUT) to work as a fast, compact, 16-bit shift register.
• Cascade LUTs to build longer shift registers.
• Implement pipeline registers and buffers for video, wireless.

Up to 1.36 Mbit Distributed RAM

• Configure any LUT to work as a single-port or dual-port 16-bit RAM/ROM.
• Cascade LUTs to build larger memories.
• Applications include flexible memory sizes, FIFOs, and buffers.

Up to 10 Mb Embedded Block RAM

• Up to 552 blocks of cascadable, synchronous 18 Kb block RAM.
• Configure any 18 Kb block as a single/dual-port RAM.
• Supports multiple aspect ratios, data-width conversion, and parity.
• Applications include data caches, deep FIFOs, and buffers.

High-Speed Memory Interfaces

• ChipSync™, SmartRAM, and Xesium clocking technologies make it easy to interface to the latest high-speed memories.

Table 1. Virtex-4 FPGA Memory Interface Support
Memory Device	Electrical Interface	Clock Rate	Data Rate
DDR2 SDRAM	SSTL 1.8V	267 MHz	534 Mbps
DDR SDRAM	SSTL 2.5V	200 MHz	400 Mbps
QDR II SRAM	HSTL 1.8V or 1.5V	300 MHz	2 x 600 Mbps
RLDRAM II	HSTL 1.8V	300 MHz	600 Mbps
FCRAM II	SSTL 1.8V	300 MHz	600 Mbps