Performance

Meet Your Performance Targets Easily

Virtex™-5 FPGAs provide the performance and design margin to easily meet your most demanding design targets with:

Table 1: System Performance Comparison
Capability Virtex-5 FPGA Virtex-4 FPGA
Fabric Performance 1.3 normalized 1.0 normalized
On-chip RAM 550 MHz 500 MHz
DSP Performance: 32-tap Filter 550 MHz 500 MHz
I/O: LVDS Bandwidth 750 Gbps 480 Gbps
I/O: Memory Bandwidth 384 Gbps 260 Gbps

ExpressFabric Technology

New ExpressFabric technology (see chart) delivers the industry’s first Real 6-LUT architecture to boost performance by two speed grades. New diagonally symmetric routing enables CLB connections through fewer switches for smaller routing delay.

On-chip Memory

Up tp 11.6 Mbits internal Block RAM, running at up to 550 MHz, allows you to buffer data for efficient processing. You can also configure these memories as 550 MHz FIFOs without consuming extra resources.

Built-in PowerPC Processor Blocks

IBM PowerPC® 400 processor blocks with APU controller and high-bandwidth crossbar switch enable implementation of area-efficient high-performance embedded processing systems based on an industry-standard architecture. The processor delivers 1,000 DMIPS at 550 MHz, for 2,200 DMIPS in a single FPGA with two processors. An innovative 5x2, 128-bit crossbar switch increases throughput by minimizing latency and enabling point-to-point connectivity. The built-in Auxiliary Processor Unit (APU) controller makes it easy to integrate custom processor-offload hardware for even higher performance.

PowerPC 440 Processor Blocks

The revolutionary FXT products deliver area-efficient, high-performance embedded systems with up to two industry-standard PowerPC® 440, 32-bit RISC processor cores, each in its own embedded peripheral block.

Each PowerPC 440 processor block contributes a 1,100 DMIPS @ 550MHz processor; you can achieve 2,200 DMIPS using a single FPGA with two processors.

Embedded DSP Blocks

The new FXT devices enable 192 GFLOPS of single-precision and 68 GFLOPS of double-precision floating-point DSP performance.

The 25 x 18 multiplier in the DSP48E slices allow single-precision floating point calculation and implementation of wide filters for a variety of DSP functions, without consuming logic fabric resources. Dedicated routing supports efficient adder-chain architectures that shatter the performance bottlenecks of adder trees.

High-Speed I/O and Memory Interfaces

With 1.25 Gbps LVDS and 800 Mbps single-ended I/O supporting a wide range of electrical standards, Virtex-5 FPGAs offer the flexibility to achieve the highest possible bandwidth for chip-to-chip, board-to-board, and box-to-box connectivity.

SelectIO™ blocks, along with ChipSync™ technology, make it easy to implement high-speed source-synchronous memory interfaces.

Performance Enhancing Technologies

Virtex-5 FPGAs ensure clock and data signal integrity by incorporating a low-skew, low-jitter 550 MHz differential clock structure. New clock management tiles offer greatly expanded flexibility by combining digital clock managers (DCM) for precise clock synthesis and phase-locked loops (PLL) for reducing jitter.

Sparse chevron packaging technology and flip-chip assembly techniques, enabled by the proprietary ASMBL™ technology and abundant PWR/GND pins, improve signal integrity by minimizing package and PCB inductance. On-chip active signal termination technology provides digitally-controlled impedance (DCI) to optimally tune component interconnects while minimizing system component count and cost.

Lower power consumption per MHz results in greater performance within your power budget. As Virtex-5 FPGAs reduce dynamic power consumption with 65nm technology, they also minimize static power consumption with triple-oxide technology.

Get the Virtex-5 FPGA Performance Advantage

To quickly and easily achieve your system performance goals you can:

 
Jobs Events Webcasts News Investors Feedback Legal Privacy Trademarks Sitemap
© 1994-2008 Xilinx, Inc. All Rights Reserved.