PCI Express Endpoint Block

      

Minimize design risk with hardened PCIe® blocks

Save time and money as you build next-generation graphics, storage, networking, and I/O devices:

• Reduce cost by integrating multiple functions into a single FPGA with built-in PCIe technology.
• Preserve software investment and extend infrastructure life with scaleable bandwidth.
• Re-target designs without changing your PCIe interface implementation.

Virtex™-5 LXT and SXT platform FPGAs contain one PCI Express® Endpoint block which implements Transaction Layer, Data Link Layer, and Physical Layer functions to provide complete PCI Express Endpoint functionality with minimal FPGA logic utilization.

Features at a Glance

• Conforms to PCI Express Base Specification 1.1
• Included on PCI-SIG® integrators list
• Supports PCI Express Endpoint or Legacy PCI Express Endpoint functions
• Designed to provide complete endpoint functionality in conjunction with RocketIO™ transceivers
• 1-, 4-, or 8-lane support per block
• Uses Block RAMs for buffering
• Fully buffered Transmit and Receive
• Management interface to access PCIe Configuration Space and internal configuration
• Full range of maximum payload size (128 to 4096 bytes) supported
• Round robin, weighted round robin, or strict priority VC arbitration
• Base Address Registers (BARs) configurable for memory or I/O
• Up to 6 x 32-bit or 3 x 64-bit BARs (or a combination of 32 bit and 64 bit)
• Statistics collection and monitoring by signaling fabric

Compliance Tested at PCI-SIG Workshops

The Xilinx PCI Express Endpoint block is on the PCI-SIG Integrators List, having successfully completed the following rigorous testing procedures of the PCI-SIG Compliance Workshop.

• FPGA Device
  • Virtex-5 LXT, Endpoint Controller, PCIe 1.0a and 1.1
  • Virtex-5 SXT, Endpoint Controller, PCIe 1.1
  • Virtex-5 FXT, Endpoint Controller, PCIe 1.1
• Reference Board
  • Virtex-5 LXT FPGA/ML505, PCIe 1.0a and 1.1
  • Virtex-5 LXT FPGA/ML523, x1, PCIe 1.0a and 1.1
  • Virtex-5 LXT FPGA/ML525, x1, PCIe 1.1
  • Virtex-5 LXT FPGA/ML555, x4x8,PCIe 1.0a and 1.1
  • Virtex-5 SXT FPGA/ML506, x1,PCIe 1.0a and 1.1
  • Virtex-5 FXT FPGA/ML507, x1,PCIe 1.1

Design Example

The following server design illustrates the PCIe topology and major components in a PCIe system. The PCI Express Endpoint block supports upstream-facing PCIe Endpoint and Legacy PCIe Endpoint blocks. The flexible configuration options of the PCIe Endpoint block, RocketIO GTP transceivers, and Block RAM enable you to build high-performance, fully-compliant PCIe systems in a single device.