RocketIO GTX Transceivers

Serial protocols at the highest line rates

Virtex™-5 FPGA system connectivity technology delivers the highest performance solutions for building high-speed, high-bandwidth connections between chips, boards, and systems.

RocketIO™ GTX transceivers for multi-gigabit serial transceiver design and proven SelectIO™ technologies for parallel I/O enable flexible bridging between emerging serial standards and existing parallel standards.

Our complete connectivity solution kits help you rapidly adopt leading edge serial protocols. Kits include:

Intellectual property cores
Design tools
Characterization reports
Documentation
Development boards

Backplane
Line card

At a Glance

High performance SERDES with 150 Mbps - 6.5 Gbps operating range supports all popular protocols
Cross-platform pin compatibility simplifies design upgrades from GTP transceivers for higher line rates
Multiple protocols (standard and custom) can be implemented in a single FPGA
Advanced 4-tap Decision Feedback Equalization (DFE) combined with linear equalization in receiver to address signal integrity challenges at high line rates
Transmitter pre-emphasis to improve signal integrity
Integrated "gear box" for flexible encoding:
8b/10b, 64b/66b, and 64b/67b
Works seamlessly with integrated PCI Express® endpoint and tri-mode Ethernet MAC blocks
Low power consumption: less than 200 mW at 6.5 Gbps
Built-in PRBS generator/checker accelerates debug

In Depth

High performance serial connectivity

The new RocketIO GTX transceiver design consumes less than 200 mW at 6.5 Gbps.

Ease of design

The RocketIO GTX transceiver wizard simplifies configuration with time-saving, menu-driven configuration for different protocol interfaces. The tool produces a wrapper, an example design, and a test bench for rapid integration and verification of the serial interface with your custom function.

A wide range of settings for Tx and Rx equalization enable you to tune transceivers for reliable operation on the toughest channels. Built-in PRBS generators and checkers simplify characterization and debug. You can rapidly zero-in on the right setting to achieve maximum design margin. These functions work with industry-standard text equipment as well as Xilinx IBERT tool which provide low-cost, easy-to-use diagnostic capabilities.

Design-specific Features

Backplane Design
Feature	Benefit
Multi-rate support	150 Mbps - 6.5 Gbps
Programmable termination	Reduces signal reflections Simplifies board design
Programmable voltage swing	Reduces power consumption
Transmit pre-emphasis	Improves signal integrity
Integrated AC coupling	Enables direct interface to other devices Reduces component count
DFE and linear receive equalization	Improves signal integrity Upgrades legacy backplanes

Line Card Design
Feature	Benefit
Multi-rate support	150 Mbps - 6.5 Gbps
FPGA fabric	Enables integration of processing components (MAC/Framer) Enables customization
Programmable Physical Coding Sublayer (PCS)	Enables support for multiple protocols in a single line card

Switching System Design
Feature	Benefit
Multi-rate support	150 Mbps - 6.5 Gbps
Up to 24 RocketIO multi-gigabit transceivers	Enables multiple port-count density points
Transmit pre-emphasis	Improves signal integrity
Receive equalization	Improves signal integrity Enables you to upgrade legacy backplanes

Server and Storage System Design
Feature	Benefit
Multi-rate support	150 Mbps - 6.5 Gbps Enables support for multiple traffic speeds in a single line card
Dynamic reconfiguration port	Enables on-the-fly updates of PMA and PCS settings
Electrical idle (out of band signaling)	Enables the link to change state PCI Express 1.1-compliant