Next generation SoC testers need to test a broader range of IO protocols, which have increasing complexity and speed. Xilinx’s SerDes and HSSIO technology offers the most flexibility at the right cost point to realize high volume SoC and Memory testers. Integrated Hard IP for memory controllers and Chip-to-Chip interconnect realize resource and cost effective solutions.
Design Examples | Description | Device Support |
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Semi-ATE: Image Acquisition |
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Semi-ATE: PIN Electronics |