The Xilinx® Alveo™ U50 Data Center accelerator cards provide optimized acceleration for workloads in financial computing, machine learning, computational storage, and data search and analytics. Built on Xilinx UltraScale+ architecture and packaged up in an efficient 75-watt, small form factor, and armed with 100 Gbps networking I/O, PCIe Gen4, and HBM, Alveo U50 is designed for deployment in any server.
Alveo accelerator cards are adaptable to changing acceleration requirements and algorithm standards, capable of accelerating any workload without changing hardware, and reduce overall cost of ownership.
Enabling Alveo accelerator cards is an ecosystem of Xilinx and partner applications for common Data Center workloads. For custom solutions, Xilinx’s Application Developer Tool Suite (Vitis™ environment) and Machine Learning Suite provide the frameworks for developers to bring differentiated applications to market.
Built for Performance & Efficiency
Adaptable – Accelerate Any Workload
Accessible - Cloud <-> On-Premises Mobility
|Board Specifications||Alveo U50 Accelerator Cards
|Look-up Tables (LUTs)||872K||872K|
|Height||½ Height||½ Height|
|Length||½ Length||½ Length|
|Width||Single Slot||Single Slot|
|HBM Memory Capacity||8 GB||8 GB|
|HBM Total Bandwidth||316 GB/s1||316 GB/s1|
|Internal SRAM Capacity||28 MB||28 MB|
|Internal SRAM Total Bandwidth||24 TB/s||19 TB/s|
|PCI Express||Gen3x 16, 2 x Gen4x 8, CCIX||
|Network Interfaces||1x QSFP28 (100GbE)||1x QSFP28 (100GbE)|
|Clock Precision||IEEE 1588||IEEE 1588|
|Vitis Developer Environment||Yes||Yes|
|Vitis Platform||Gen3x16 XDMA, Gen3x4 XDMA3||Gen3x4 XDMA4|
|Vivado Design Suite||Yes||Yes|
|Power and Thermal|
|Maximum Total Power||75W||75W|
|Target Workloads||Fintech, Video, Database & Computational Storage||Machine Learning(ML) Inference|
Note 1: For A-U50-P00G-PQ-G and A-U50-P00G-LV-G measured 316 GB/s peak HBM2 bandwidth, 201 GB/s nominal
Note 2: A-U50-P00G-LV-G card requires a PCI Express x16 slot for the edge connector and supply of 75W
Note 3: A-U50-P00G-PQ-G card with VCCINT core voltage set to Vccint=0.85v supports PCIe Gen3x4 deployment platform shells for XLNX Video solution
Note 4: A-U50-P00G-LV-G card with VCCINT core voltage set to Vccint=0.72v supports PCIe Gen3x4 deployment platform shells for XLNX Vitis AI solution
We’ve developed an ecosystem of Xilinx and partner solutions for most common workloads. Alveo Data Center accelerator cards can deliver dramatic acceleration across a broad set of applications and are reconfigurable to provide an ideal fit for the changing workloads of the modern data center. Compare how Alveo Data Center accelerator cards perform compared to traditional CPU architectures.
The preferred optimal design flow for targeting the Alveo Data Center accelerator card uses the Vitis™ software platform. Steps to deploy and develop using Vitis are given below. Long-time FPGA designers might want to use traditional design flows, such as RTL or HLx. This flow does not require installing the Vitis platform.
To install the Alveo card and deploy applications, follow the instructions in the Card Install Guide. Download links for the Xilinx Runtime and Deployment Target Platform, needed during card installation, are given below.
The Xilinx runtime (XRT) is a low level communication layer (APIs and drivers) between the host and the card.
IMPORTANT: Please enter the following command before installing the XRT:
$ sudo yum-config-manager --enable rhel-7-server-optional-rpms
$ sudo yum install -y https://dl.fedoraproject.org/pub/epel/epel-release-latest-7.noarch.rpm
$ sudo yum install epel-release
The deployment target platform is the communication layer physically implemented and flashed into the card.
To develop Alveo accelerated applications, follow the software installation instructions in the Vitis Development Installation Guide. The Vitis design environment and development target platform download links are given below.
The target platform interface for development is required if you are building your own applications.
For development using RTL and HLx, follow these steps: