2. Intellectual Property
  3. Integrated Logic Analyzer (ILA) with AXIS Interface

Integrated Logic Analyzer (ILA) with AXIS Interface

Overview

Product Description

The Integrated Logic Analyzer (ILA) IP with AXIS interface is a configurable logic analyzer core that can debug and monitor internal signals and AXI interfaces within a design. The ILA core includes many advanced features such as Boolean trigger equations and edge transition triggers. It can not only be used for triggering on events and capturing the data from internal signals but also be used for transaction-level debug of one or more AXI interfaces (AXI4-MM or AXI4-S).

The ILA IP has a dedicated AXIS interface for connection to a debug master interface or core (such as Debug Hub) for software communication and control/status management.

Key Features and Benefits

  • Configurable trigger ports, which can be combined into a single trigger condition
  • User-selectable trigger width and capture data depth
  • Supports transaction-level debug of AXI interfacesn
  • Protocol Checking capability for AXI interfaces
  • Cross-triggering input/output ports

Support

Device Family:

Design Tools:

Documentation

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