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10G Ethernet with 1588 Subsystem

  • Part Number:
  • Bundled With:
    • Vivado Design Suite
  • License: End User License Agreement

Product Description

For UltraScale and UltraScale+ device support, refer to the 10G/25G Ethernet Subsystem

The 10 Gigabit Ethernet subsytem provides a 10 Gigabit Ethernet MAC and PCS/PMA in 10GBASE-R/KR modes to provide a 10 Gigabit Ethernet port. The transmit and receive data interfaces use AXI4-Stream interfaces. An optional AXI4-Lite interface is used for the control interface to internal registers.

The 10G Ethernet IP core enables 1-step and 2-step 1588 hardware time stamping delivered through IP Integrator with 10GBASE-R. This IP core utilizes the Xilinx 10G Ethernet MAC IP core connected to the 10GBASE-R or 10GBASE-KR IP.The control interface to internal registers is via a 32-bit AXI Lite Interface.The transmit and receive data interface is via the AXI4-Streaming interface. There is no additional charge for access to the 10G Ethernet Subsystem. However, 10G Ethernet MAC and 10GBASE-KR are fee based IP cores and you will need to have the proper licensing keys based upon your configuration requirements.

Key Features and Benefits

  • AXI4-Stream protocol support on client TX and RX interfaces
  • Configured and monitored through an optional AXI-Lite Management Data interface or using status and configuration vectors
  • Supports 10GBASE-SR, -LR and -ER optical links in Zynq-7000, Virtex-7 and Kintex-7 devices, and UltraScale devices (LAN mode only)
  • Supports 10GBASE-KR backplane links including Auto-Negotiation (AN), Training and Forward Error Correction (FEC)
  • Supports Deficit Idle Count
  • Comprehensive statistics gathering
  • Supports 802.3 and 802.1Qbb flow control
  • Supports VLAN and jumbo frames
  • Customer Preamble mode
  • Independent TX and RX Maximum Transmission Unit (MTU) frame length
  • Supports high accuracy IEEE Standard 1588-2008 1-step and 2-step timestamping on a 10GBASE-R network interface
  • For 7-Series and legacy UltraScale designs please refer to the Documentation tab on this page

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