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Spartan-3 FPGA
High Logic and I/O Count
Spartan®-3 FPGAs offer platform capabilities with a wide range of I/O and density options. The Spartan-3 platform solution targets high logic/ pin count designs and applications.
What's in Spartan-3 FPGA?
- Eight devices ranging from 50 K system gates to 5 M system gates
- Up to 104 Dual Port Block RAM - configurations from 1 to 36 bits wide
- Up to 104 embedded 18 x 18 multipliers that can be used with or without the BRAMs for DSP and complex math
- Digital Clock Managers (DCM) for precision clocking and clock synthesis
- XCITE technology which eliminates external termination resistors and simplifies PCB layout while lowering the BOM
- Configuration using Platform Flash with bitstream compression.
The leading connectivity platform
- Allows the ability to migrate to a larger or smaller device within the same package, without changing the pin out as the design changes
- Supports most popular and emerging single-ended and differential signaling standards including PCI and LVDS
- Up to 633 I/O pins
- Staggered I/O technology which increases the number of I/O per device compared to the competition
Low cost DSP solutions
- 1.8 billion multiply and accumulates (MACs) per second
- Up to 104 18x18 embedded multipliers for implementing compact DSP structures such as MAC engines, and adaptive and fully parallel FIR filters
- SRL16 shift register logic and distributed memory for building compact DSP structures such as filters
- Block RAM for storing partial products and coefficients
- Complex DSP algorithms, such as Forward Error Correction (FEC) codecs, filters, for digital communications and imaging applications
- Common functions such as a single channel, 64-tap FIR filter running at 8.1 MSPS that can be implemented for an effective cost
Configurable logic blocks
- Two slices per CLB – Four LUT / registers per CLB plus extra carry logic for math and logic functions
- Wide-input functions – 8:1 mux in one CLB
- Fast arithmetic functions – Two look-ahead carry chains per CLB column
- Four cascadable 16-bit addressable shift registers
Multi-level memory architecture
- Up to 520 Kb Distributed SelectRAM+™ Memory
- Up to 1.87 Mb Embedded Block RAM
- Popular external memory Interfaces
Precise clock management resources
- All digital delay-locked loop (DLL) in each DCM
- Up to 4 Digital Clock Managers (DCMs) per device
- Flexible frequency generation from 5 MHz to 333 MHz
- Precision phase shift control for 0, 90, 180 or 270 degrees
- Fine grain control (1/256 clock period) for clock data synchronization
- Precise 50/50 duty cycle generation
Why Spartan-3 FPGA?
Lowest total cost. Period.
- Delivers lowest total cost
- Industry's largest selection of device/package options
- Industry's most comprehensive IP library
- Leading embedded and DSP solutions
- Efficient, cost-effective board designs
- Allows use of fewer standard components
- Increased system reliability by eliminating external components
Low-cost Embedded Processing platform
Complete design solution for optimal results
- ISE® Foundation™ software
The industry's most complete programmable logic design solution for optimal performance, power management, cost reduction, and productivity
- ISE WebPACK™ software
Our free, easy-to-use logic design solution for your Xilinx CPLD or medium-density FPGA, with all the tools included in ISE Foundation, on both Windows and Linux
- ISE Classics software
A free collection of previously released ISE software tools
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