Spartan-3A

Spartan®-3A FPGA Family Data Sheet, including Overview, Specifications, and Pinouts. See the Spartan-3 Generation User Guides for additional information.

Excel file to calculate DFS output jitter based on input and output clock frequencies. Applies to Spartan®-3A, Spartan-3AN, and Spartan-3A DSP platforms.

This document introduces the Extended Spartan®-3A family of FPGAs. It provides features, a device summary, functional overview, packaging options, and ordering information for the device family.

Comma-delimited ASCII text files and Excel footprints for each package type in the Extended Spartan®-3A Family (Spartan-3A, Spartan-3AN, and Spartan-3A DSP platforms).

Functional description of the Spartan®-3 generation FPGA architecture and how to use it. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 platforms.

Describes the configuration features of the Spartan®-3 Generation FPGAs. Includes the Spartan-3A, Spartan-3AN, Spartan-3A DSP, Spartan-3E, and Spartan-3 FPGA families.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

Spartan™-3A XC3S700A Errata for Engineering Samples

Spartan™-3A XC3S1400A Errata for Engineering Samples

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

The purpose of this Quality Alert is to communicate that the Non-continuous Slave Parallel (SelectMAP) or ICAP_SPARTAN3A data loading via de-asserting CSI_B does not function as expected, and is not a supported feature of these devices.

This notice is to announce the standardization of remaining Spartan®-3A devices to the current 2-layer substrate for the FT256 and FTG256 packages.

Design File(s):

• Qualification Report for XCN08014
• FAQ for XCN08014

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

To announce the transitioning of all wire bond package types for Spartan®-3, Spartan-3E and Spartan-3A FPGA products from gold (Au) to copper (Cu) wire.

This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan®-3A FPGA using iMPACT 9.1.01i. The hardware setup, software flows for file generation, and programming are also covered.

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

Design File(s):

• xapp457.zip

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

Design File(s):

• xapp500.zip

This Application Note describes the feature of Platform Flash PROMs that allows the user to Multiple-Boot or dynamically reconfigure from up to four Design Revisions.

Design File(s):

• xapp483.zip

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

Design File(s):

• xapp491.zip
• xapp491.zip

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

Design File(s):

• xapp482.zip
• xapp482.zip

The Spartan-3A/3AN/3A DSP FPGA families offer an advanced static power management feature called Suspend mode, which reduces FPGA power consumption while retaining the FPGA’s configuration data and maintaining the application state. The device can quickly enter and exit Suspend mode as required in an application.

The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following: • Reduce total system cost by using less expensive devices • Achieve higher data transfer rates than allowed by specification • Add more loads to the bus to accommodate additional devices and connectors • Increase the physical length of the bus to accommodate novel bus topologies The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

Design File(s):

• xapp229.zip
• xapp229.zip

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Design File(s):

• xapp224.zip
• xapp224.zip

This application note outlines how to successfully configure a Spartan™-3A FPGA from a Platform Flash PROM. Including hardware requirements and software flows for generating and programming PROM files.

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Design File(s):

• xapp689.zip

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

Design File(s):

• xapp1002.zip

This document details the design aspects of digital PLLs implemented in Virtex® and Spartan® FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

Design File(s):

• xapp868.zip

Describes how Extended Spartan®-3A family and Spartan-3E FPGAs work in spread-spectrum applications.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note describes a reference design that adds fail-safe mechanisms to the MultiBoot capabilities of the Extended Spartan®-3A family of FPGAs. The reference design configures specific FPGA logic via an initial bitstream that determines which application to load.

Design File(s):

• xapp468.zip

The DDR2-400 (200 MHz clock) memory interface discussed in this application note is derived from the default output of MIG. Xilinx has validated this interface in Spartan®-3A FPGAs with the higher speed grade (-5) assembled on Spartan-3A Starter Kits. The validation results also apply to Spartan-3AN and Spartan-3A DSP FPGAs.

Design File(s):

• xapp458.zip

This application note describes how the existing dual-port block memories in the Spartan®-II and Virtex® families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Design File(s):

• xapp228.zip

The block memories in the Virtex®-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

Design File(s):

• xapp291.zip

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

Design File(s):

• xapp502.zip

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with all Xilinx solutions for PCI Express®.

Design File(s):

• xapp1022.zip

This application note targets Spartan®-3E/3A devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp485.zip

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

Design File(s):

• xapp486.zip
• xapp486.zip

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/Os in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses parasitic leakage current behavior.

This Application Note describes a set of reference designs that can transmit and receive DVI or HDMI data streams up to 750 Mb/s using the native TMDS I/O featured by Spartan®-3A FPGAs.

Design File(s):

• xapp460.zip

This application note discusses how to design and implement a Bus Master design using Xilinx® Endpoint PCI Express® solutions. A performance demonstration reference design using Bus Mastering is included with this application note. The reference design can be used to gauge achievable performance in various systems and act as a starting point for an application-specific Bus Master Direct Memory Access (DMA). The reference design includes all files necessary to target the Integrated Blocks for PCI Express on the Virtex®-6 and Spartan®-6 FPGAs, the Endpoint Block Plus Wrapper Core for PCI Express using the Virtex-5 FPGA Integrated Block for PCI Express, and the Endpoint PIPE for PCI Express targeting the Xilinx Spartan®-3 family of devices.

Design File(s):

• xapp1052.zip

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG400 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FG484 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A CPG132 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A PQG208 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A TGQ144 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A TQ144 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A CPQ208 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/3E/3A CP132 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan -3/-3E/-3A FGG900 (Cu Wire) Packages

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FG900 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG484 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG400 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG320 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A VQ100 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A VQG100 (Cu Wire)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG320 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

FGG320 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)

Design File(s):

• IPC-1752 Form

FG320 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FT256 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FTG256 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG676 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FG676 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FG1156 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG1156 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FG456 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for Spartan®-3/-3E/-3A FGG456 (Cu Wire) Package

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Report summarizes the results of the reliability stress tests performed to qualify copper wire for use in wire-bonded packages.

This white paper identifies the top design security threats, explores the advanced security options, and describes how new, low-cost Spartan™-3A, Spartan-3AN, and Spartan-3A DSP FPGAs from Xilinx can help protect your products and profits.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

FPGAs can be configured with test applications during the development and production test stage. This white paper explores efficient options to help in product development and accelerate testing on the production line.

This white paper describes methods for expanding the natural bit-width capability of dedicated multipliers in a way that will make best use of the complete FPGA resources.

Operating logic at a higher rate than the processing rate allows operations to be achieved sequentially. As with a processor, logic is timeshared over multiple clock cycles. Memory holds values not being used on a given clock cycle. The FPGA can be considered to be a three-dimensional volume to be filled. "Performance + Time = Memory" is a strange formula, but when understood, it can often result in significantly lower cost implementations with Xilinx devices.

This white paper examines the causes of jitter, jitter measurement techniques, and methods of managing jitter in digital systems.

This white paper describes design techniques that improve signal integrity in Xilinx® FPGAs.

This white paper defines the use and limitations of bit error ratio measurements when analyzing the performance of communications links.

This white paper discusses the FPD market and looks in closer detail at Plasma Display Panels and Liquid Crystal Displays in particular. An overview of where Xilinx devices fit in digital video systems is followed by a market overview of the flat panel display industry. The value proposition for Xilinx devices is presented, followed by a detailed discussion of the relationship of product features and resources to FPD system requirements.

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

This document provides a concise overview of the subset of the MATLAB language, including operators, as well as built-in and toolbox functions supported by AccelDSP™ Synthesis Tool for algorithmic synthesis targeting Xilinx FPGAs.

This white paper identifies the top design security threats, explores the basic levels of security, and describes how new, low-cost Spartan®-3A, Spartan-3AN, and Spartan-3A DSP FPGAs from Xilinx can help protect your products and profits.

Applying a global reset to your FPGA designs is not a very good idea and should be avoided. This is a controversial issue, so this white paper looks at the reasons why such a design policy should be considered.

This white paper defines IBIS models and describes how to use them to model I/O characteristics for Xilinx® FPGAs.

This white paper examines alternate uses of available block RAM in Virtex® and Spartan® FPGAs.

This White Paper describes how Spartan®-3 FPGAs can reduce total system cost by up to 50% compared to competing FPGAs.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.

This white paper describes the steps necessary to analyze your design's power requirements using the Xilinx® Power Estimator.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

Using Xilinx Spartan™-3E and Spartan-3A FPGAs, a National Semiconductor PHY, and a Xilinx video processing stack provides a very cost-effective and flexible approach to the challenges of multi-rate broadcast.

This white paper provides examples to help your understanding of the capabilities and use of the SRL16E to improve the performance and lower the cost of your designs by as much as an order of magnitude.

This white paper discusses signal analysis requirements and methods for printed circuit board design for Xilinx® FPGAs.

This white paper considers a variety of ways in which multiplexers can be implemented within Xilinx FPGA devices, including some alternative techniques that can lead to more efficient and lower cost implementations.

Modern CMOS processes with their smaller geometries cause certain undesirable side effects. These issues are reviewed with respect to their effect on system design using ASSP, ASIC, or FPGA devices, and what Xilinx has done to alleviate the potential problem.

This user guide describes the components and operation of the Spartan™-3A/3AN FPGA Starter Kit Board, for Revision D. The Starter Kit provides a low-cost, easy-to-use development and evaluation platform for Spartan-3A/3AN FPGA designs.

Design File(s):

• Reference Designs

Describes the original Revision C Spartan™-3A FPGA Starter Kit Board. See UG334 for the Revision D board.

Design File(s):

• Reference Designs

Spartan™-3A/3AN FPGA Starter Kit board schematics.

Design File(s):

• s3astarter_bom.xls

Gerber board layout plots in PDF format for the Spartan™-3A and Spartan™-3AN FPGA Starter Kit boards.

This guide provides information about how to use the Video Starter Kit (VSK) to begin experimenting with video processing using the Spartan®-3A DSP family of FPGAs.