Spartan-3A

The J Drive programming engine provides immediate and direct in-system configuration (ISC) support for IEEE Standard 1532 programmable logic devices (PLDs). To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language (BSDL) file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port (TAP). The J Drive executable, source code, and a programming example are available in a download package from the Xilinx website. The J Drive programming engine can be used for the following Xilinx families: CoolRunner-II CPLDs, XC9500/XL/XV CPLDs, Spartan-3 Generation FPGAs, and Virtex-II (and later) series FPGAs.

Differential signals, such as LVDS or LVPECL, can be difficult to route on simple, four-layer or six-layer PCBs without excessive use of vias. This application note shows how Spartan™-3 Generation FPGAs, with just the inclusion of an inverter in the datapath, can avoid excessive use of vias and fix accidental PCB trace swapping without requiring a PCB respin.

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit transmit data bus widths and operate at rates up to 666 Mbps per line with a forwarded clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

This application note targets Spartan™-3E devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications.

This Application Note describes the feature of Platform Flash PROMs that allows the user to Multiple-Boot or dynamically reconfigure from up to four Design Revisions.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

The Spartan-3A/3AN/3A DSP FPGA families offer an advanced static power management feature called Suspend mode, which reduces FPGA power consumption while retaining the FPGA’s configuration data and maintaining the application state. The device can quickly enter and exit Suspend mode as required in an application.

The PCI™ Local Bus Specification defines a number of power and reset requirements. When considered in an FPGA implementation, these create several challenges that must be addressed for long term reliability and broad interoperability. This application note applies to compliant PCI applications using Spartan™-3 Generation FPGAs, and is relevant to other Xilinx FPGA families, as well as related PCI applications.

The PCI specification defines two I/O timing budgets for use with 33 MHz and 66 MHz operation. In embedded designs, custom timing budgets enable the following: • Reduce total system cost by using less expensive devices • Achieve higher data transfer rates than allowed by specification • Add more loads to the bus to accommodate additional devices and connectors • Increase the physical length of the bus to accommodate novel bus topologies The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices.

This application note describes how memories wider than 36 bits can be efficiently implemented in the Virtex™-II and Spartan™-3 architectures. The clock-doubling method used is similar to the method described for quad-port memories in XAPP228. The resulting memories are used in either dual-port or single-port mode.

This application note describes how the existing dual-port block memories in the Spartan™-II and Virtex™ families can be used as Quad-Port memories. This essentially involves a data access time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the block memory in terms of bits per second will remain the same.

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

The block memories in the Virtex™-II architecture are capable of supporting data bus widths of up to 36-bits. A self-addressing FIFO reference design uses these block memories to store both data and address information in a single memory location. This application note describes FIFO designs where no external counters are required. Only flag and status information logic is used. The resulting FIFOs are not fast (around 150 MHz). Their advantage is in using only one clock load. In addition, the status mechanism is very simple making FIFOs are more suitable for data throttling in continuous data systems instead of the full or empty detection required in frame-based data systems.

This application note outlines how to successfully configure a Spartan™-3A FPGA from a Platform Flash PROM. Including hardware requirements and software flows for generating and programming PROM files.

This application note describes how to indirectly program an SPI Serial Flash PROM through the JTAG interface of a Spartan™-3A FPGA using iMPACT 9.1.01i. The hardware setup, software flows for file generation, and programming are also covered.

This application note discusses the use of Partitions in the Incremental Design Flow. It is recommended that module instances with high logic density, timing critical paths, or timing critical module instances be designated Partitions.

This application note discusses the Serial Peripheral Interface (SPI) configuration mode introduced in the Virtex™-5 and Spartan™-3E FPGA families. The ISE™ iMPACT in-system programming solution with the Xilinx cables for prototype designs is described.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

This application note covers the principles of power distribution systems and bypass or decoupling capacitors. A step-by-step process is described where a power distribution system can be designed and verified. The final section discusses additional sources of power supply noise and provides resolutions.

This document provides information for debugging board level problems by using ChipScope™ Pro with Endpoint for PCI Express designs using Virtex™-4, Virtex-5, Virtex-II Pro FPGAs, the Endpoint PIPE for PCIe core using Spartan™-3/-3E/-3A FPGAs, and in the Endpoint Block Plus for PCIe core with Virtex-5 devices.

The DDR2-400 (200 MHz clock) memory interface discussed in this application note is derived from the default output of MIG. Xilinx has validated this interface in Spartan™-3A FPGAs with the higher speed grade (-5) assembled on Spartan-3A Starter Kits. The validation results also apply to Spartan-3AN and Spartan-3A DSP FPGAs.

This application note discusses using the provided Memory Endpoint Test (MET) demonstration driver to exercise the Programmed Input/Output (PIO) design that is delivered with the Endpoint Block Plus Wrapper, Endpoint, and Endpoint PIPE for PCI Express® Xilinx solutions.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

In embedded systems, designers can reduce component count and increase flexibility by using a microprocessor to configure an FPGA. C code illustrates the use of either Slave Serial or SelectMAP mode. CPLD design files illustrate a synchronous interface between processor and FPGA.

This document details the design aspects of digital PLLs implemented in Virtex™ and Spartan™ FPGAs for telecommunications applications. PLL performance and loop stability are evaluated.

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/O in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses the parasitic leakage current behavior.

This white paper identifies the top design security threats, explores the advanced security options, and describes how new, low-cost Spartan™-3A, Spartan-3AN, and Spartan-3A DSP FPGAs from Xilinx can help protect your products and profits.

This white paper identifies the top design security threats, explores the basic levels of security, and describes how new, low-cost Spartan®-3A, Spartan-3AN, and Spartan-3A DSP FPGAs from Xilinx can help protect your products and profits.

This white paper discusses the various memory interface controller design challenges and Xilinx solutions, including how to use the Xilinx software tools and hardware-verified reference designs to build a complete memory interface solution for your own application, from low-cost DDR SDRAM applications to higher-performance interfaces like the 667Mb/s DDR2 SDRAMs.

This white paper reviews the potential inaccuracies associated with the traditional one-resistor approach to selecting heatsinks, and suggests a more accurate two-resistor (2-R) approach based on both theta-jc and theta-jb from the device datasheet.

This document provides a concise overview of the subset of the MATLAB language, including operators, as well as built-in and toolbox functions supported by AccelDSP™ Synthesis Tool for algorithmic synthesis targeting Xilinx FPGAs.

This white paper discusses the FPD market and looks in closer detail at Plasma Display Panels and Liquid Crystal Displays in particular. An overview of where Xilinx devices fit in digital video systems is followed by a market overview of the flat panel display industry. The value proposition for Xilinx devices is presented, followed by a detailed discussion of the relationship of product features and resources to FPD system requirements.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

Using Xilinx Spartan™-3E and Spartan-3A FPGAs, a National Semiconductor PHY, and a Xilinx video processing stack provides a very cost-effective and flexible approach to the challenges of multi-rate broadcast.

FPGAs can be configured with test applications during the development and production test stage. This white paper explores efficient options to help in product development and accelerate testing on the production line.

Applying a global reset to your FPGA designs is not a very good idea and should be avoided. This is a controversial issue, so this white paper looks at the reasons why such a design policy should be considered.

This white paper considers a variety of ways in which multiplexers can be implemented within Xilinx FPGA devices, including some alternative techniques that can lead to more efficient and lower cost implementations.

Operating logic at a higher rate than the processing rate allows operations to be achieved sequentially. As with a processor, logic is timeshared over multiple clock cycles. Memory holds values not being used on a given clock cycle. The FPGA can be considered to be a three-dimensional volume to be filled. "Performance + Time = Memory" is a strange formula, but when understood, it can often result in significantly lower cost implementations with Xilinx devices.

This white paper discusses signal analysis requirements and methods for printed circuit board design for Xilinx® FPGAs.

This white paper examines the causes of jitter, jitter measurement techniques, and methods of managing jitter in digital systems.

This white paper defines IBIS models and describes how to use them to model I/O characteristics for Xilinx® FPGAs.

This white paper defines the use and limitations of bit error ratio measurements when analyzing the performance of communications links.