Spartan-6

This overview outlines the features and product selection of the Spartan®-6 family.

This data sheet contains the DC and switching characteristic specifications for the commercial Spartan®-6 family including the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs.

All packages are ASCII files in txt format.

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This document provides reference information about the I/O buffer information specification algorithmic modeling interface (IBIS-AMI) Signal Integrity Simulation Kit and the Tx and Rx control parameters available to the user.

This guide describes the function and operation of the Spartan®-6 FPGA Integrated Block for PCI Express®, including how to design, customize, and implement it. This document contains information about the AXI4 version of the core.

This User Guide describes the function and operation of the Spartan®-6 FPGA Integrated Endpoint Block for PCI Express®, including how to design, customize, and implement it.

Summary of the reliability test data and results for Xilinx devices updated four times per year.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the SelectIO™ resources available in all Spartan®-6 FPGAs.

This guide describes the clocking resources available in all Spartan®-6 FPGAs, including the DCMs and PLLs.

This guide describes the Spartan®-6 FPGA block RAM capabilities.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan®-6 FPGAs.

This guide describes the usage and implementation of the GTP transceivers available in the Spartan®-6 LXT FPGAs.

This guide describes the DSP48A1 slice available in Spartan®-6 FPGAs.

This guide provides information on PCB design for Spartan®-6 devices, with a focus on strategies for making decisions at the PCB and the interface level.

This user guide provides information on the various hardware methods of power management in Spartan®-6 FPGAs, primarily focusing on the suspend mode.

The Spartan®-6 FPGA GTP Transceiver Signal Integrity Simulation (SIS) Kit for Mentor Graphics HyperLynx provides a simulation environment for evaluating channel designs for Spartan-6 FPGA GTP transceivers. This document describes how to install the SIS kit and get started with simulations.

This guide describes the Spartan®-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System. This Answer Record lists the Design Advisories that have been communicated for the Spartan-6 FPGA products.  

This Answer Record describes the Known Issues for the Spartan-6 FPGA family used with ISE Design Suite 13. 

EN113: Errata for Spartan®-6 LX16 CES FPGAs.

EN115: Errata for Spartan®-6 LX150 CES FPGAs.

EN117: Errata for Spartan®-6 LX45 CES FPGAs.

EN118: Errata for Spartan®-6 LX45T CES FPGAs.

EN124: Errata for Spartan®-6 LX150T CES FPGAs.

EN146: Errata for the Spartan®-6 FPGA LX4, LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9953 devices.

EN147: Errata for the Spartan®-6 FPGA LX9, LX16, LX25/T, LX45/T, LX75/T, LX100/T, and LX150/T CES9951 devices.

EN148: Errata for the Spartan®-6 FPGA production devices.

EN168: Errata for the Lower Power Spartan®-6 FPGA LX production devices.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate that Xilinx is discontinuing the -4 speed grade of Spartan®-6 LXT family devices and moving existing customers to the new, upgraded -3 speed grade devices.

The purpose of this notification is to inform Xilinx customers of a change to the Memory Controller Block (MCB) performance, an update to the JTAG ID Revision Code, a change to the maximum ICCINTQ and ICCAUXQ specifications, and an update to the CSG324 Bank 0/2 SSO limit recommendations for “XC” Commercial Spartan®-6 LX16 -2C and Spartan-6 LX45 -2C FPGA production devices.

To communicate a mask change for all production Spartan®-6 FPGA devices and a speed file change for all Spartan-6 –3N speed devices.

To inform Xilinx customers of corrections in UG383 to the described behavior of the configuration-time initialization and configuration readback operations specific to the 9 Kb configuration of the Spartan®-6 FPGA block RAM.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

This notification is to inform Xilinx customers of changes to the Spartan-6® FPGA speed files in the ISE® Design Suite v13.3 and later.

This application note describes an in-the-field upgrade of the Spartan®-6 FPGA bitstream, Linux kernel, and loader flash images, using the presently running Linux kernel.

Design File(s):

• xapp1146.zip

This application note discusses how to efficiently use the Spartan®-6 FPGA ISERDES and OSERDES primitives in conjunction with the input delay blocks and phase-detector circuitry.

Design File(s):

• xapp1064.zip

This application note and associated reference design describes how to merge the operation of two or more Memory Controller Blocks (MCBs) to implement effective 32-bit or wider memory interfaces in Spartan®-6 FPGAs.

Design File(s):

• xapp496.zip

This application note extends the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD to support Aurora 8B/10B serial protocol.

Design File(s):

• xapp492_S6_ConnectivityTRD_Aurora.zip

This application note describes a set of reference designs able to transmit and receive DVI and HDMI data streams up to 1080 Mb/s using the native TMDS I/O interface featured by Spartan®-6 FPGAs.

This document describes how to implement triple-rate SDI interfaces using Spartan®-6 FPGAs.

Design File(s):

• xapp1076_S6GTP_TripleRateSDI.zip

This application note and reference design gives examples of a typical spread-spectrum clock for video applications using the Spartan®-6 FPGA DCM_CLKGEN primitive. DCM_CLKGEN can be used for fixed spread-spectrum generation without any logic or in a soft spread-spectrum solution using a state machine.

Design File(s):

• xapp1065.zip

This application note describes the implementation of a DisplayPort™ source core and policy maker reference design targeted for the Spartan®-6 FPGA Consumer Video Kit (CVK).

Design File(s):

• xapp493_DisplayPort_SPM.zip

This application note describes the implementation of a DisplayPort&trade sink core and policy maker reference design targeted for the Spartan®-6 FPGA Consumer Video Kit (CVK).

Design File(s):

• xapp593_DisplayPort_Sink.zip

This application note discusses how to design and implement a Bus Master design using Xilinx® Endpoint PCI Express® solutions. A performance demonstration reference design using Bus Mastering is included with this application note. The reference design can be used to gauge achievable performance in various systems and act as a starting point for an application-specific Bus Master Direct Memory Access (DMA). The reference design includes all files necessary to target the Integrated Blocks for PCI Express on the Virtex®-6 and Spartan®-6 FPGAs, the Endpoint Block Plus Wrapper Core for PCI Express using the Virtex-5 FPGA Integrated Block for PCI Express, and the Endpoint PIPE for PCI Express targeting the Xilinx Spartan®-3 family of devices.

Design File(s):

• xapp1052.zip

This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan®-6 FPGA Phase Locked Loop (PLL) through its Dynamic Reconfiguration Port (DRP).

Design File(s):

• xapp879.zip

This application note includes a method for sharing an internal configuration access port (ICAP) between the user design and the soft error mitigation (SEM) controller in the Spartan®-6 and Virtex®-6 devices.

Design File(s):

• xapp517_DualUse_ICAP_SEM.zip

This application note details bridging an XSVI interface to an AXI4-Stream interface, enabling video designs with Xilinx video IP cores and XSVI interfaces to use the AXI VDMA.

Design File(s):

• xapp521.zip

Package Drawing.

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet FGG484

Design File(s):

• Material Composition Declaration, FGG484 (IPC-1752 Format)

Design File(s):

• Material Composition Declaration, CSG225 (IPC-1752 Format)

Material Declaration Data Sheet, FG676 Package for Spartan-6 FPGAs

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet, FGG676 Package for Spartan-6 FPGAs.

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet FTG256 Package for Spartan-6 FPGAs

Design File(s):

• IPC-1752 Form

196 Ball Chip-Scale BGA (CPG196) Package

100% Material Declaration Data Sheet: CSG324

Design File(s):

• IPC-1752 Form

Material Declaration Data Sheet for the CSG484 package for the Spartan®-6 FPGA.

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet for CS324 Package

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet, FGG900 Package for Spartan®-6 FPGA

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet, FG900 Package for Spartan®-6 FPGAs

Design File(s):

• IPC-1752 Form

100% Material Declaration Data Sheet CPG196 for Spartan®-6 FPGAs

Design File(s):

• IPC-1752 Form

This characterization report compares the electrical performance of the Spartan®-6 FPGA GTP transceiver against the PCI Express® Revision 1.1 specifications published in the PCI Express Base Specification, Revision 1.1 and the PCI Express Card Electromechanical Specification, Revision 1.1. All testing for this report is based on a line rate of 2.5 Gb/s across voltage, temperature, and worst-case transceiver performance corners.

This white paper addresses where and when to use DO-254 and DO-178 in FPGA designs and recommends practical means for employing widely used COTS IP in custom FPGA designs that target avionics applications.

This white paper highlights concerns regarding effects of SEEs on ASICs and FPGAs and points to analysis and mitigation techniques for handling SEEs.

The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. Xilinx® Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

Targeted design platforms are simpler, smarter, and more strategically viable design platforms that offer customers the optimum in flexibility, accessibility, applicability, and time to market.

This white paper discusses targeting guidelines and other considerations needed to achieve optimal designs with Spartan®-6 devices.

FPGAs enabled with serial I/O offer the ideal balance of bandwidth, density, performance, flexibility, and cost for SoC designs. Xilinx offers a portfolio of serial I/O technology that addresses the full spectrum of bandwidth requirements for products ranging from commercial video displays to broadcast video ultra-high bandwidth wired telecommunications systems.

This white paper discusses how synthesis and implementation can help to optimize the performance of Spartan®-6 designs.

The FPGA Mezzanine Card (FMC) standard, developed by a consortium of companies ranging from FPGA vendors to end users, specifically targets FPGAs, increasing I/O flexibility and lowering costs in a broad range of applications.

This white paper describes the Virtex®-6 FPGA Connectivity Kit (DK-V6-CONN-G) and the Spartan®-6 FPGA Connectivity Kit (DK-S6-CONN-G) that engineers can use to jump-start their connectivity-based designs.

The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

This white paper discusses the observed performance of the Spartan®-6 FPGA Connectivity targeted reference design. The design uses PCI Express®, Ethernet, and an integrated memory controller along with a packet DMA for moving data between system memory and the FPGA.

ISE® Design Suite v12 is the production-optimized tool suite for Virtex®-6 and Spartan®-6 FPGAs that delivers innovation in three critical areas of FPGA design: power reduction, productivity, and performance.

Xilinx delivers the first automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30% for Virtex®-6, Spartan®-6, Kintex™-7 and Virtex-7 FPGA designs.

This white paper describes how design engineers can take advantage of Virtex®-6, Spartan®-6, and 7 series FPGAs to handle the complexity of designing portable ultrasound systems and bring cutting-edge ultrasound technology to market quickly within cost and power constraints.

The AXI4 specification represents a major evolutionary step in interconnect technology for on-chip system design. The value of the AXI4 interconnect has many facets, beginning with an immediate gain in productivity derived from a unified IP interconnect standard that supplants legacy and custom interconnect architectures. The three interconnect protocols developed for the AXI4 standard (AXI4, AXI4-Lite, and AXI4-Stream interfaces) provide the flexibility to optimize an FPGA design for performance, throughput, latency, or area.

Xilinx DSP Targeted Design Platforms enable the optimization of DSP processing and system performance, price/performance, and productivity for the broadest possible range of DSP designs and design team expertise.

The purpose of this white paper is to describe how Spartan®-6 FPGAs address the needs of high-volume systems. The ability to connect efficiently and inexpensively to commodity memories, high-performance chip-to-chip interface capability, and innovative power down modes are just a few of the problems solved by high-performance, low-power, and low-cost Spartan-6 FPGAs.