Spartan-6

This data sheet contains the DC and switching characteristic specifications for the Spartan®-6 family.

This overview outlines the features and product selection of the Spartan®-6 family.

All packages are ASCII files in txt format.

This guide describes the usage and implementation of the GTP transceivers available in the Spartan®-6 LXT FPGAs.

This advance specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

This guide describes the SelectIO™ resources available in all Spartan®-6 FPGAs.

This guide describes the clocking resources available in all Spartan®-6 FPGAs, including the DCMs and PLLs.

This guide describes the Spartan®-6 FPGA block RAM capabilities.

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan®-6 FPGAs.

This guide describes the DSP48A1 slice available in Spartan®-6 FPGAs.

This guide describes the Spartan®-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards.

This guide provides information on PCB design for Spartan®-6 devices, with a focus on strategies for making decisions at the PCB and the interface level.

Results of the most recent tests for reliability of Xilinx® devices. Xilinx publishes this report to provide customers with test data and results regarding the reliability of Xilinx products.

EN124: rrata for Spartan®-6 LX150T CES FPGAs.

EN113: Errata for Spartan®-6 LX16 CES FPGAs.

EN115: Errata for Spartan®-6 LX150 CES FPGAs.

EN117: Errata for Spartan®-6 LX45 CES FPGAs.

EN118: Errata for Spartan®-6 LX45T CES FPGAs.

100% Material Declaration Data Sheet: CSG324

Package Drawing.

パッケージ図面

Targeted design platforms are simpler, smarter, and more strategically viable design platforms that offer customers the optimum in flexibility, accessibility, applicability, and time to market.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. Spartan®-6 and Virtex®-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

The FPGA Mezzanine Card (FMC) standard, developed by a consortium of companies ranging from FPGA vendors to end users, specifically targets FPGAs, increasing I/O flexibility and lowering costs in a broad range of applications.

FPGAs enabled with serial I/O offer the ideal balance of bandwidth, density, performance, flexibility, and cost for SoC designs. Xilinx offers a portfolio of serial I/O technology that addresses the full spectrum of bandwidth requirements for products ranging from commercial video displays to broadcast video ultra-high bandwidth wired telecommunications systems.

This white paper discusses targeting guidelines and other considerations needed to achieve optimal designs with Spartan®-6 devices.