Spartan-IIE

All four modules of Spartan-IIE FPGA family data sheet in one Acrobat PDF file for easy searching.

Xilinx is implementing a Warehouse Management System (WMS) in its internal warehouses worldwide. As a result, a license plate number (LPN), which is a unique tracking number, will now appear on labels beginning in August 2007. There are no changes to the form, fit, or function of the product.

The purpose of this notice is to communicate that Xilinx is discontinuing certain Q-grade extended temperature range products.

The purpose of this notice is to announce the addition of STATS ChipPAC in Singapore (SCS) as a qualified assembly partner for Plastic Quad Flat Pack (PQFP), Thin Quad Flat Pack (TQFP/VQFP), and Ball Grid Array in wire bond (BGA) packages.

Design File(s):

• Qualification Report for XCN06016

Xilinx is temporarily changing the MSL level on certain devices in the Pb-free FTG256 package from Level 3 to Level 5 per JEDEC STD-020C due to moisture-induced delamination failures.

This notification describes a material set consolidation of mold compound and die-attach epoxy across various packages in all Xilinx device families. The new material set is already used in Xilinx RoHS-compliant products. There is no change to the form, fit, or function of the devices.

Design File(s):

• Qualification Report for XCN05011

Xilinx is changing from a 6 dot HIC to a 3 dot HIC to comply with industry standard dry packing requirements, JEDEC standard J-STD-033.

Dual marking is being introduced for "-7C" and "-6I" Spartan-IIE devices, whereby these products will now have a "-7C/-6I" marking.

Xilinx is changing the primary supplier for Ball Grid Array (BGA) shipping trays from Peak to both Daewon and Kostat.

To advice customers that Xilinx has added alternate shipping tray for 28mm x 28mm QFP packages and 31mm x 31mm BGA packages.

To inform customers of a change to the Humidity Indicator Card (HIC). There is no change to the form, fit, or function.

To communicate the addition of new supply sources for wire bond BGA package core and prepreg material for Spartan®/-XL/-II/-IIE/-3/-3E/-3A/-3AN/-3ADSP/-6, XC95XXX, XC95XXXXL, Virtex®, Virtex®-E, Virtex®-II/-ll Pro, and CoolRunner™ and CoolRunner™-II product.

To communicate that the Xilinx discontinuation of certain Virtex® (Virtex-E, Virtex-EM, Virtex-II and EasyPath™ Virtex-II families) and Spartan® (Spartan-IIE family) FPGA products has been retracted due to a two year extension of production capability.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

Design File(s):

• xapp800.zip

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

Design File(s):

• xapp693.zip
• xapp693.zip

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

Design File(s):

• xapp689.zip

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

Design File(s):

• xapp482.zip
• xapp482.zip

Some FPGAs require a minimum supply current in order to power on. For many applications, power supplies selected to cover operating current requirements can readily source enough instantaneous current to satisfy the power-on current requirement. For other applications, there may be a strict limit on the available supply current. The addition of a large capacitor and a few other passive components permit power-on with less supply current than the power-on specification requires. This application note presents a number of these “power-assist” solutions.

Design File(s):

• xapp451.xls
• xapp451.xls

FPGAs require a minimum supply current in order to power on. This application note explains the nature of the current, the implications of the power-on current specifications, and the major factors that influence the current. Board-level considerations and regulator selection follow. The last section introduces an approach to FPGA power-on in the presence of an overcurrent protection circuit.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

Design File(s):

• xapp441_designfiles.zip
• xapp441_designfiles.zip

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock, i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known. The circuit described in this application note addresses this issue for both single traces and data buses up to 210 MHz in a Virtex®-II -5 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Digital Clock Manager (DCM), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Design File(s):

• xapp225.zip

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

Design File(s):

• xapp224.zip
• xapp224.zip

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

Design File(s):

• xapp223.zip

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

Design File(s):

• xapp211.zip
• xapp211.zip

Power consumption in Xilinx Spartan™-II FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. It is common for a large, high-speed design to require one Ampere or more of current. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turnoff are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered in order to achieve successful designs.

This application note demonstrates using a Boundary Scan (JTAG) interface to configure and read back Spartan®-II and Spartan-IIE FPGA devices. Xilinx FPGAs have Boundary Scan features that are compatible with the IEEE Standard 1149.1. This application note is a complement to the configuration section in the Data Sheets and Application Note XAPP176.

The Spartan™-II and Spartan-IIE FPGA families simplify high-performance design by offering SelectIO™ inputs and outputs with programmable interface standards. This application note describes how to take full advantage of the flexibility of the SelectIO features and the design considerations to improve and simplify system-level design.

This application note describes a simple CPLD-based interface design that configures a Spartan™-II device from a parallel EPROM using the Slave Parallel configuration mode.

This application note is offered as complementary text to the configuration section of the Spartan®-II and Spartan-IIE data sheets and provides a complete description of the configuration process and flow. Each of the configuration modes are outlined and discussed in detail, concluding with a complete description of data stream formats, and readback functions and operations.

The Spartan™-II FPGAs provide dedicated blocks of true dual-port RAM, known as Block SelectRAM+™ memory. This dedicated memory provides a cost-effective use of resources without sacrificing the existing distributed SelectRAM memory or logic resources. The Block SelectRAM+ memory is fully synchronous for easy timing analysis and is easily initialized at configuration. This additional integration capability makes the Spartan-II family ideal for cost-sensitive applications.

The Xilinx high-performance CPLD, FPGA, and configuration PROM families provide in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and still keep the original device pin-outs, which eliminates the need to re-tool PC boards.

Design File(s):

• xapp058.zip

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

Design File(s):

• xapp694.zip

The Spartan®-II and Spartan-IIE families provide fully digital Delay-Locked Loop (DLL) circuits, which provide zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control. These dedicated DLLs can be used to implement several circuits that improve and simplify system-level design.

Design File(s):

• xapp174.zip

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx® devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

This application note explains how to use the Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

Design File(s):

• xapp551.zip

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design. This product is not recommended for new designs.

Design File(s):

• xapp933.zip

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan® and Virtex® FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function. This product is not recommended for new designs.

Design File(s):

• xapp634.zip

This application note describes the implementation of R’G’B’ Color Space to Y’CbCr Color Space conversion necessary in many video designs. The tick marks on red, green, blue, and Luma, assume the components are in the gamma-corrected space. No gamma correction is applied to color difference signals Cr and Cb. This product is not recommended for new designs.

Design File(s):

• xapp637.zip

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design. This product is not recommended for new designs.

Design File(s):

• xapp529_6_1.zip
• xapp529_6_2.zip

This application note discusses the enormous strides made by Spartan™ series FPGAs in terms of density and performance and how it should be viewed as the Gate Array replacement. The Spartan device family offers many of the features that are desired by Gate Array designers with the major advantage of programmability, which can prove to be the key factor in the success of the product.

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

Design File(s):

• IPC-1752 Form

This paper discusses the overall purpose of OFFSET constraints, the specific paths that are covered by OFFSET constraints, and the differences between the OFFSET IN and OFFSET OUT constraints.

This white paper compares and contrasts FPGA and microprocessor system design and development flows with the aim of helping the designer and definer of state-of-the-art electronics systems to make a considered and well informed architecture decision.

Surface Mount Technology (SMT) packages include the leaded family packages (Quad Flat Pack (QFP) and Plastic Leaded Chip Carrier (PLCC)) and the Ball Grid Array (BGA) packages. SMT rework can be necessary for any of the following reasons: assembly related defects, such as shorts, opens, wrong orientation, and solder ball defects; device/package related defects/failure analysis; and engineering change or system upgrade.

Describes how PCB design considerations play a major role in obtaining the expected performance from FPGAs. Focuses on early analysis and simulation methodologies as a way of performing a guided implementation. If design variables are analyzed and results passed to implementation, it is more likely the desired specifications will be met in the first pass, fulfilling the ultimate goal to keep development effort, cost, and time to a minimum.

Obsolescence is a concern of most design engineers and none more so than with automotive telematics equipment designers. Even though automotive electronics equipment design and development time scales have shrunk recently from 5 to 2 years, the products themselves will still need to be produced for many years and be active in the field or even longer.

The Xilinx Field Programmable Controller (FPC) solution allows you to create low-cost, customized processors with peripherals, memory, and logic — all on a single cost-optimized Spartan™-IIE FPGA. The FPC solution is ideal for applications in which cost and integration within a system is critical. With the flexibility to allow integration of other IP on the FPGA fabric, the Spartan-IIE family presents an ideal embedded solution. This white paper presents the end markets, FPC solution, and its associated tools, end applications, and the Spartan-IIE performance advantage.

Focuses on how Xilinx enables the automobile to be a more entertaining, more informative, and more productive environment. When we envisage automotive electronics we automatically consider electric windows, central locking systems, safety systems, climate control and electronic ignition systems, all of which require stringent qualification, temperature cycling, and certification. The new emerging automotive electronics boon has now shifted from under the hood or bonnet to in-cabin multimedia applications. The trend towards mobile offices and entertainment on the move has meant a large portion of the electronic or semiconductor content has moved into this expanding area.

This white paper describes a rarely noticed design technique that can make a difference in the size and the performance of your FPGA design. Control signals on FPGA flip-flops have a built-in priority. If you can learn to write code that is sympathetic to the priorities, the results will be rewarding. This white paper provides some simple VHDL and Verilog examples to explain key points.

FPGAs can be configured with test applications during the development and production test stage. This white paper explores efficient options to help in product development and accelerate testing on the production line.

Applying a global reset to your FPGA designs is not a very good idea and should be avoided. This is a controversial issue, so this white paper looks at the reasons why such a design policy should be considered.

This white paper considers a variety of ways in which multiplexers can be implemented within Xilinx FPGA devices, including some alternative techniques that can lead to more efficient and lower cost implementations.

Operating logic at a higher rate than the processing rate allows operations to be achieved sequentially. As with a processor, logic is timeshared over multiple clock cycles. Memory holds values not being used on a given clock cycle. The FPGA can be considered to be a three-dimensional volume to be filled. "Performance + Time = Memory" is a strange formula, but when understood, it can often result in significantly lower cost implementations with Xilinx devices.

This white paper examines how to remove the DC content from a digitally sampled waveform using DSP without complicated mathematics.