Spartan-IIE

This application note provides a Xilinx FPGA solution to two-dimensional filtering with a parameterized VHDL reference design.

This application note describes a method to configure Xilinx FPGAs, such as Spartan®-IIE and Spartan-3 FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories.

This application note describes how to retrieve user-defined data from Xilinx configuration PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the FPGA. The method to add user-defined data to the configuration PROM file is also discussed.

This application note illustrates the use of a Xilinx CoolRunner-II™ CPLD to monitor configuration data between a Xilinx Platform Flash Configuration PROM and a Xilinx Spartan™ or Virtex™ family FPGA. The intent is to ensure reliable configuration of the FPGA while providing revision control for one or more configuration files stored in the PROM.

Ground bounce must be controlled to ensure proper operation of high performance FPGA devices. Particular attention must be applied to minimizing board-level inductance during PCB layout. This document describes calculations that help to ensure that a design meets input undershoot and logic-low voltage requirements for devices receiving signals from an FPGA.

This application note describes a full-featured transmitter/receiver macro that can communicate with Spartan™ and Virtex™ FPGA families via the Analog Devices ADSP-TS101S TigerSHARC™ link-port function.

Huffman coding is used to code values statistically according to their probability of occurence. Short code words are assigned to highly probable values and long code words to less probable values. Huffman coding is used in MPEG-2 to further compress the bitstream. This application note describes how Huffman coding is done in MPEG-2 and its implementation.

This application note describes a reference design to do a quantization and inverse quantization of MPEG-2 video signals. After a brief introduction, the process of using JPEG and MPEG-2 standards for quantizing matrices is developed. Finally, implementing the Xilinx solution for quantization or inverse quantization is described.

This application note describes a two-dimensional Inverse Discrete Cosine Transform (2D IDCT) function implemented on a Xilinx FPGA. The reference design file provides behavioral code for implementation on any Xilinx device.

This application note describes a two-dimensional Discrete Cosine Transform (2D DCT) function implemented on a Xilinx® FPGA. The reference design file provides behavioral code for implementation on any Xilinx device.

The Cyclic Redundancy Check (CRC) is a powerful technique to obtain data reliability. This application note discusses the implementation of Configurable CRC Modules with LocalLink interfaces. The user can tailor the features of these modules to suit the protocol or application that is implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules.

This application note explains how to use the Xilinx Viterbi Decoder LogiCORE™ module (version 5.0 or later) to implement both trellis termination and tail biting.

MicroBlaze™ has the ability to use its dedicated FSL bus interface to integrate a customized IP core into a MicroBlaze soft processor-based system. This document describes possible methods to include customized IP cores into an SCP-based design.

This application note provides users with a general understanding of the SVF and XSVF file formats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) is assumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format (XSVF) files in embedded programming applications, refer to Xilinx Application Note XAPP058.

This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families.

XAPP482 describes a working MicroBlaze™ system that stores software code, user data, and configuration data in non-volatile Platform Flash PROMs, simplifying system design and reducing cost. It provides a portable hardware design, software design, and additional script utilities to be used during the implementation flow.

Some FPGAs require a minimum supply current in order to power on. For many applications, power supplies selected to cover operating current requirements can readily source enough instantaneous current to satisfy the power-on current requirement. For other applications, there may be a strict limit on the available supply current. The addition of a large capacitor and a few other passive components permit power-on with less supply current than the power-on specification requires. This application note presents a number of these “power-assist” solutions.

FPGAs require a minimum supply current in order to power on. This application note explains the nature of the current, the implications of the power-on current specifications, and the major factors that influence the current. Board-level considerations and regulator selection follow. The last section introduces an approach to FPGA power-on in the presence of an over-current protection circuit.

This application note describes techniques for remote reconfiguration of FPGAs through an Ethernet port.

One of the most significant variables that can affect the package warpage is the solder reflow process. This application note discusses the details of the solder reflow process and provides guidelines on profiling to achieve successful reflow of BGA components.

Verification is an integral part of any FPGA design project. Many older verification models are no longer appropriate to the new multimillion-gate FPGAs, and more modern methods must be brought to bear if verification is to positively affect product time to market. The methodologies used for designing and implementing a good verification plan are discussed in detail, in the context of a real-world verification case study.

This application note describes three ways to implement the Y'CrCb Color Space to R'G'B' Color Space conversion necessary in many video designs.

This application note and reference design outline a method to implement clock and data recovery in Virtex™-II devices. Although not limiting the implementation to a specific FPGA family, this reference design focuses on the Virtex-II architecture. With minor modifications, Clock and Data Recovery (CDR) is possible with Virtex-E and Spartan™-IIE devices. A implementation of CDR at 270 Mb/s with 8B/10B coded data is described herein.

This application note describes how to use Virtex™-E Bus Low Voltage Differential Signaling (BLVDS) technology in high-performance multipoint applications. BLVDS extends the benefits of standard LVDS into multipoint configuration supporting bidirectional backplanes. Spice simulation results show that the multipoint configuration described in this application note can operate up to 200 MHz.

This document describes an implementation of a low-overhead data synchronization and framing method to use with the LVDS capability of Virtex™-E devices described in XAPP233.

This application note describes how to use differential LVPECL (low-voltage positive emitter-coupled logic) signaling for high-performance multi-drop applications with Virtex™-E FPGAs. Multi-drop LVPECL allows a single LVPECL driver to connect directly to multiple LVPECL receivers on a single transmission line. SPICE simulations verify multi-drop operation from DC up to 311 Mbits/s, with ten loads. This application note includes DC specifications, and an Appendix with microstrip and layout guidelines. The LVPECL receivers on the Virtex-E FPGA eliminate costly LVPECL-TTL translators, reducing board area and skew.

Systems that include two or more FPGAs often require high-bandwidth data paths between devices. As the clock period and switching times of digital circuits become shorter, straightforward methods of transferring data between devices are often inadequate. At high frequencies, signal propagation delay and reflections that occur in conductors just a few centimeters long must be taken into account. The SelectLink™ communications channel utilizes special features of the Virtex™ family, including Delay Locked Loops, Block SelectRAM+, and SelectI/O, to create a system that can move large amounts of data between FPGAs at very high speeds. A code generation tool available at www.xilinx.com allows logic designers everywhere to instantly create customized SelectLink Verilog source code. The modules are easily instantiated in the designers top-level code for a complete system solution.

This application note describes how to use the Virtex™ -E LVDS (low-voltage differential signaling) drivers and receivers for high-performance LVDS interfaces to industry-standard LVDS devices. LVDS provides higher noise immunity than single-ended techniques, allowing for higher transmission speeds, smaller signal swings, lower power consumption, and less electromagnetic interference than single-ended signaling. Differential data can be transmitted at these rates using inexpensive connectors and cables. Virtex-E LVDS drivers offer improved signal integrity over other LVDS drivers because they absorb reflected signals.

This application note describes the use of LVDS signaling for high-performance multi-drop applications with Virtex™ -E FPGAs. Multi-drop LVDS allows many receivers to be driven by one Virtex-E LVDS driver. Simulation results indicate that the reference design described here will operate from DC up to 311 Mbits/s. This application note includes DC specifications, microstrip and layout guidelines.

This application note describes the LVDS I/O standard. LVDS provides higher noise immunity than single-ended techniques, allowing for higher transmission speeds, smaller signal swings, lower power consumption, and less electro-magnetic interference than single-ended signaling. Differential data can be transmitted at these rates using inexpensive connectors and cables. LVDS provides robust signaling for high-speed data transmission between chassis, boards, and peripherals using standard ribbon cables and IDC connectors with 100 mil header pins. Point-to-point LVDS signaling is possible at speeds of up to 622 Mb/s.

When designing digital systems, there is often a requirement to synchronize incoming data and clock signals with an internal system clock (i.e., the internal and external clock are at exactly the same frequency, but due to variable backplane, board, or application-specific standard product (ASSP) delays, the phase relationship is not known). The circuit described in this application note addresses this issue for both single traces and data busses up to 160 MHz in a Virtex™-E, -7 device. The speed limitation is imposed by the maximum frequency that can be accepted by the Data Locked Loop (DLL), in a mode where it is capable of providing both a new clock and a new clock shifted by 90 degrees.

Data recovery is a mechanism that allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts this information from the data stream concerned, but sometimes the receiver’s clock is used for data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™-E -7 device, a Spartan™-IIE -6 device, or a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro™ -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Delay Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.

This application note describes highly optimized UART transmitter and receiver macros for Xilinx Virtex®, Virtex-E, and Spartan®-II devices. The UART_TX and UART_RX macros are fully compatible with the standard Universal Asynchronous Receiver Transmitter (UART) communication protocols used for connecting to devices, such as PCs or microcontrollers.

The convolutional interleaver technique is used in telecommunication applications such as SDH and PDH radio systems, GSM and UMTS mobile communication systems, and point-to-multipoint radio systems to protect transmission channels from noise. On the transmit side, the convolutional interleaver parallelizes serial input data into N-bit words and shifts the data word through N delay lines. The delayed data is then shifted out through a PISO shift register for transmission. At the receiver, the incoming data stream is reconstructed with dual-delay lines and shift registers.

Linear Feedback Shift Registers (LFSRs) are commonly used in applications where pseudo-random bit streams are required. LFSRs are the functional building blocks of circuits like the pseudo-random noise (PN) code generator (XAPP211) and Gold code generators (XAPP217) commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an LFSR using the SRL16 (Shift Register Look-Up Table) primitive for area-efficient designs. The first LFSR implementation describes the parallel output access and parity calculation; the second describes the multi-cycle output access and sequential parity calculation. This application note covers the Virtex™ series, the Virtex™-II series, and the Spartan™-II family of devices.

This application note describes a high-speed, reconfigurable, full-precision Transposed Form FIR filter design implemented in the Virtex™ and Virtex™-II series and Spartan™-II family of FPGAs. The VHDL reference design provided with this application note is easily modified to change filter parameters including coefficients and the number of taps. By illustrating a design methodology for digital filters, the advantages of using FPGAs for digital signal processing applications (DSP) are emphasized. The CORE Generator™ tool provides a preoptimized alternative solution to this reference design.

Gold code generators are used extensively in Code Division Multiple Access (CDMA) systems to generate code sequences with good correlation properties. This application note describes the implementation of Gold code generators in Virtex™>, Virtex™-E, Virtex™-EM, Virtex™-II and Spartan™-II devices. The Gold code generators use efficiently-implemented Linear Feedback Shift Registers (LFSRs) in both the Virtex/Virtex-II series and Spartan-II family using the SRL16 macro.

The Constant (k) Coded Programmable State Machine (KCPSM) presented in this application note is a fully embedded 8-bit microcontroller macro for the Virtex™ and Spartan™-II devices. The module is remarkably small at just 35 CLBs, less than half of the smallest Spartan™ XC2S15 device, and virtually free in an XCV2000 device by consuming less than 0.37% of the device CLB.

Code Division Multiple Access (CDMA) is a rapidly expanding data transmission technique in the emerging Universal Mobile Telecommunications System (UMTS). This application note describes the implementation of a CDMA matched filter using the architectural features of the Virtex™ series, Virtex™-II series, and Spartan™-II family of devices.

Pseudo-random Noise (PN) generators are at the heart of every spread spectrum system. Many PN generators are required within Code Division Multiple Access (CDMA) base stations. PN generators are used to implement synchronization and uniquely code individual user signals across the transmission interface. PN generators are based upon Linear Feedback Shift Registers (LFSRs). Every Look-Up-Table (LUT) in a Virtex™ series or Virtex™-II series device can be configured as a 16-bit shift register (SRL16 macro). Hence, Virtex devices implement efficient LFSRs and deliver a significant reduction in resource utilization when compared with alternative flip-flop-only PLD structures.

This application note describes the design and implementation of a simple, low-cost interface to the Dallas Semiconductor’s 1-Wire devices in Virtex™ and Spartan™-II families to acquire the 64-bit ROM number. The number is available in either eight sequential byte transfers through an 8-bit data port, or a 48-bit latched parallel output. A typical application is to use the 48-bit serial number in the ROM number as the physical address of a network interface. This reference design is synthesizable and utilizes only 52 registers, 65 look-up tables (LUTs), and 55 slices of FPGA resource.

This application note describes a reference design for a Virtex™-E FPGA interface to an Intel Pentium™ processor. The Pentium I™ system bus, design concerns, and possible applications of this design are discussed. Additionally, the differences between the Pentium I, II, and III busses are discussed. For more information specific to the Intel Pentium family of processors, see the Intel developer web site (http://developer.intel.com/).

Power consumption in Xilinx Spartan™-II FPGAs depends upon the number of internal logic transitions and is proportional to the operating clock frequency. As device size increases, so does power consumption. It is common for a large, high-speed design to require one Ampere or more of current. Without an accurate thermal analysis, the heat generated could easily exceed the maximum allowable junction temperature. Power supply requirements, including initial conditions, transient behavior, turn-on, and turnoff are also important. Bypassing or decoupling the power supplies at the device, in the context of the device’s application, requires careful attention. All these aspects of the power supply must be considered in order to achieve successful designs.

This application note demonstrates using a Boundary Scan (JTAG) interface to configure and read back Spartan™-II and Spartan-IIE FPGA devices. Xilinx FPGAs have Boundary Scan features that are compatible with the IEEE Standard 1149.1. This application note is a complement to the configuration section in the Data Sheets and Application Note XAPP176.

The Spartan™-II and Spartan-IIE FPGA families simplify high-performance design by offering SelectIO™ inputs and outputs with programmable interface standards. This application note describes how to take full advantage of the flexibility of the SelectIO features and the design considerations to improve and simplify system-level design.

This application note describes a simple CPLD-based interface design that configures a Spartan™-II device from a parallel EPROM using the Slave Parallel configuration mode.