XAPP501 - Configuration Quick Start Guidelines (PDF)
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This application note discusses the configuration and programming options for Xilinx Complex Programmable Logic Device (CPLD), Field Programmable Gate Array (FPGA), and PROM families and demonstrates some of the most popular configuration methods used for each family. This document includes configuration quick start guidelines for the Virtex™, Spartan™, XPLA3, XC9500, and XC18V00 families. Was this document helpful? Yes | No
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1.5 |
249 KB |
10/02/2007 |
XAPP126 - Data Generation and Configuration for Spartan Series FPGAs (PDF)
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This application note describes various methods to configure Spartan™ series FPGAs. Each configuration method is described in detail. Information on necessary software programs to run with input files required, output files produced, download cables used, and other hardware necessary to accomplish the task is discussed. This application note targets users who are new to Xilinx® devices and Alliance/Foundation series software tools and is intended to make the configuration and debugging flows easy to understand. Was this document helpful? Yes | No
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1.1 |
138 KB |
07/22/2003 |
XAPP125 - Conserving Power With Auto Power Down Mode in Spartan-XL FPGAs (PDF)
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Power consumption plays an important role in battery-powered applications. Spartan™-XL FPGAs are designed with segmented routing, 3.3-V operation, and advanced process technology to meet the needs for low power and high performance. This application note shows how to reduce power consumption by selectively disabling portions of the design that are not required all the time. This approach is particularly useful for devices that must be operating at all times. This application note discusses different strategies for reducing the supply current incrementally for an operating device. Was this document helpful? Yes | No
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1.1 |
21 KB |
03/22/1999 |
XAPP124 - Using Manual Power Down Mode With Spartan-XL FPGAs (PDF)
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Spartan™-XL FPGAs come equipped with a Power Down mode that permits an exceptionally low level of power consumption (ICCO = 100 µA typical), making the family ideal for portable battery-powered applications. This application note provides all the information needed for a designer to use Power Down mode effectively, including descriptions of the mode's common applications, internal functioning and electrical characteristics. Was this document helpful? Yes | No
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1.1 |
26 KB |
03/22/1999 |
XAPP122 - The Express Configuration of Spartan-XL FPGAs (PDF)
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This application note provides information on how to perform Express configuration for the Spartan™-XL family. Express Mode uses an eight-bit-wide bus for fast configuration of Xilinx FPGAs. The steps of Express configuration are described, followed by detailed circuit implementation instructions. Was this document helpful? Yes | No
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3.0 |
111 KB |
04/20/2001 |
XAPP120 - Spartan FPGAs--The Gate Array Solution (PDF)
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This application note discusses the enormous strides made by Spartan™ series FPGAs in terms of density and performance and how it should be viewed as the Gate Array replacement. The Spartan device family offers many of the features that are desired by Gate Array designers with the major advantage of programmability, which can prove to be the key factor in the success of the product. Was this document helpful? Yes | No
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2.0 |
87 KB |
08/01/2001 |
XAPP119 - Adapting ASIC Designs for Use with Spartan FPGAs (PDF)
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Spartan™ FPGAs are an exciting alternative for implementing digital designs that, previously, would have employed ASIC technology. Pre-existing ASIC intellectual property can be adapted for use with Spartan devices by following a straightforward procedure. Each step of the procedure is explained in detail. Guidelines show how an ASIC design, in the form of an RTL-level HDL file, can be revised to take full advantage of the Spartan series capabilities, thereby achieving efficient, high-performance implementations. Was this document helpful? Yes | No
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1.0 |
57 KB |
07/20/1998 |
XAPP098 - The Low-Cost, Efficient Serial Configuration of Spartan FPGAs (PDF)
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This application note describes how to achieve low-cost serial configuration for Spartan™/Spartan™-XL FPGA designs, including: taking advantage of unused resources in a design (thereby reducing cost), part count, memory size, and board space. The idle processing time of an on-board controller is used to load configuration data from an off-board source, which allows a Spartan design to be upgraded in the field by sending the bitstream over a network. Was this document helpful? Yes | No
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1.0 |
97 KB |
11/13/1998 |
XAPP091 - Configuring Mixed FPGA Daisy Chains (PDF)
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Xilinx FPGAs can be configured in a common daisy chain structure, where the lead device generates CCLK pulses and feeds serial configuration information into the next downstream device, which in turn feeds data into the next downstream device, etc. There is no limit to the number of devices in a daisy chain, and XC3000™, XC4000™, Spartan™, and XC5200™-series devices can be mixed freely with only one constraint: the lead device must be a member of the highest order family used in the chain. Was this document helpful? Yes | No
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1.0 |
26 KB |
11/24/1997 |
XAPP090 - FPGA Configuration Guidelines (PDF)
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These guidelines describe the configuration process for all members of the XC3000™, XC4000™, XC5200™, and Spartan™ FPGA devices and their derivatives. The average user need not understand or remember all these details, but should refer to the debugging hints when problems occur. Was this document helpful? Yes | No
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1.1 |
58 KB |
11/24/1997 |
XAPP088 - I/O Characteristics of XL FPGAs (PDF)
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Data sheets describe I/O parameters in digital terms, providing tested and guaranteed worst-case values. This application note describes XC4000XL/XLA and Spartan™-XL I/O parameters in analog terms, giving the designer a better understanding of the circuit behavior. However, such parameters are not production-tested and are, therefore, not guaranteed. Was this document helpful? Yes | No
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1.0 |
30 KB |
11/24/1997 |
XAPP052 - Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators (PDF)
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Shift registers longer than eight bits can be efficiently implemented in XC4000™ or Spartan™ series SelectRAM memory. Using Linear Feedback Shift Register (LFSR) counters to address the RAM makes the design even simpler. This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers, and pseudo-random sequence generators with repetition rates of thousands and even trillions of years, useful for testing and encryption purposes. The appropriate taps for maximum-length LFSR counters of up to 168 bits are listed. Was this document helpful? Yes | No
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1.1 |
101 KB |
07/07/1996 |
XAPP051 - Synchronous and Asynchronous FIFO Designs (PDF)
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This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000™ Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. Emphasis is on the fast, efficient and reliable generation of the handshake signals FULL and EMPTY, which determine design performance. Was this document helpful? Yes | No
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2.0 |
106 KB |
09/17/1996 |
XAPP017 - Boundary Scan in XC4000/XC5200 Device (PDF)
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XC4000/XC5200/Spartan FPGA devices contain boundary scan facilities that are compatible with IEEE Standard 1149.1. This application note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design. Was this document helpful? Yes | No
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3.0 |
214 KB |
11/16/1999 |
XAPP015 - Using the XC4000 Readback Capability (PDF)
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This application note describes the XC4000/Spartan™ Readback capability and its use. Topics include: initialization of the Readback feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading back FPGA devices, and Cyclic Redundancy Check (CRC). Was this document helpful? Yes | No
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1.0 |
58 KB |
11/01/1995 |