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Partial Reconfiguration in the Vivado Design Suite

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs offer. The use of Partial Reconfiguration can allow designers to move to fewer or smaller devices, reduce power, and improve system upgradability. Make more efficient use of the silicon by only loading in functionality that is needed at any point in time.

Partial Reconfiguration Software

The current software approach, which has been in production since Vivado® Design Suite 2013.3, builds upon the robust solution introduced in ISE® Design Suite in 2010. The software tools unlock the capability to reconfigure a portion of a Xilinx FPGA while the rest of the device remains operational. This current solution utilizes the Tcl-based non-project flow and leverages the impressive implementation capabilities of the Vivado Design Suite. RTL-based designs are supported in project mode within the Vivado IDE, with many underlying flow details automatically managed.

The Partial Reconfiguration flow in the Vivado Design Suite has the following features:

  • Powerful Working Environment
    • Tcl-based non-project flow from HDL to bitstream, and RTL project mode support in the Vivado IDE
    • Efficient management of databases for static and reconfigurable modules
    • Black box bitstream support, allowing incomplete modules to be omitted
  • User is in Control
    • User decides how to manage reconfigurable module variants
    • Keep the static design open in memory while modules are swapped in and out
    • Floorplan determines what resources are reconfigured
  • Low level details are handled by the software
    • Tools manage Partition interfaces automatically, with no overhead
    • Design Rule Checks (DRCs) validate design structure and configurations
    • Standard timing closure techniques applied

All 7 series, Zynq and UltraScale devices support Partial Reconfiguration. UltraScale support is complete, with all devices supported through bitstream generation in the current Vivado Design Suite version. Contact Xilinx for access to the VU440. UltraScale+ device support begins with Vivado Design Suite version 2016.3, with initial access for seven devices.

UltraScale represents a new breakthrough in Partial Reconfiguration technology, enabling reconfiguration of nearly all FPGA resource types, including I/O, Gigabit Transceivers, and clocking networks.

Partial Reconfiguration is available as a product within the Vivado Design Suite. Contact your local sales offices for pricing and ordering details.

Professors and researchers associated with universities may receive licenses through the Xilinx University Program (XUP).  Learn more about access requirements and procedures for obtaining licenses here.

Key Technology Benefits

  • Increase solution flexibility by time-multiplexing design functionality
  • Reduce FPGA size or count (and therefore cost) by time-sharing functionality
  • Reduce dynamic power consumption by loading functions on-demand

Key Software Features

  • Supports complete design implementation using robust Partition technology
  • Allows full design constraint entry, timing analysis and verification
  • Supports Virtex-7, Kintex-7, Artix-7, Virtex UltraScale, Kintex UltraScale, Virtex UltraScale+ and Kintex UltraScale+ FPGAs
  • Supports Zynq®-7000 All Programmable SoCs and Zynq UltraScale+ MPSoC devices
Partial Reconfiguration Survey

Partial Reconfiguration Survey

Using Xilinx Partial Reconfiguration in your design?  Considering Partial Reconfiguration for an upcoming project?  We want to hear from you!  Take the Xilinx Partial Reconfiguration Survey and share your feedback and feature requests.