We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Partial Reconfiguration in the Vivado Design Suite

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. Xilinx Partial Reconfiguration technology allows designers to change functionality on the fly, eliminating the need to fully reconfigure and re-establish links, dramatically enhancing the flexibility that FPGAs offer. The use of Partial Reconfiguration can allow designers to move to fewer or smaller devices, reduce power, and improve system upgradability. Make more efficient use of the silicon by only loading in functionality that is needed at any point in time.

Partial Reconfiguration Software

The current software approach, which has been in production since Vivado® Design Suite 2013.3, builds upon the robust solution introduced in ISE® Design Suite in 2010. The software tools unlock the capability to reconfigure a portion of a Xilinx FPGA while the rest of the device remains operational. The current solution leverages the impressive implementation capabilities of the Vivado Design Suite. Users can implement designs using the Tcl-based non-project flow, and now RTL-based designs are supported in project mode within the Vivado IDE, with many underlying flow details automatically managed.

Four pieces of intellectual property are available to help designers complete Partial Reconfiguration designs more quickly and easily.  The Partial Reconfiguration Controller IP is a hardware-based configuration controller that can help manage all aspects of reconfiguration events, from triggering and arbitration to bitstream delivery and error handling.  The Partial Reconfiguration Decoupler IP can be used with the PR Controller or with any customer controller to safely isolate the dynamic region as it is being reconfigured. The Partial Reconfiguration AXI Shutdown Manager IP helps users cease activity on AXI interfaces so Reconfigurable Partitions can be safely reconfigured.  The Partial Reconfiguration Bitstream Monitor IP allows users to debug and monitor partial bitstreams, ensuring version and target compatibility.

Partial Reconfiguration is now included at no additional cost within Vivado Design Suite HLx System and Design Editions. The Partial Reconfiguration feature is also available for purchase for WebPack additions, at a new lower cost.  Contact your local sales offices for pricing and ordering details.

Key Features and Benefits

Powerful Working Environment

  • Tcl-based non-project flow from HDL to bitstream, and RTL project mode support in the Vivado IDE
  • Efficient management of databases for static and reconfigurable modules
  • Black box bitstream support, allowing incomplete modules to be omitted

User is in Control

  • User decides how to manage reconfigurable module variants
  • Keep the static design open in memory while modules are swapped in and out
  • Floorplan determines what resources are reconfigured

Low level details are handled by the software

  • Tools manage Partition interfaces automatically, with no overhead
  • Design Rule Checks (DRCs) validate design structure and configurations
  • Standard timing closure techniques applied

Partial Reconfiguration is now included at no additional cost within Vivado® Design Suite HLx System and Design Editions. The Partial Reconfiguration feature is also available for purchase for Vivado WebPack™ Edition, at a new lower cost.

Most 7 series and Zynq®-7000 devices support Partial Reconfiguration, with the only exceptions being the smallest devices within these families. UltraScale™ support is complete, with all devices supported through bitstream generation in the current Vivado Design Suite version. Contact Xilinx for access to the VU440. UltraScale+™ device support covers nearly all devices in production. See the Partial Reconfiguration User Guide (UG909) for the complete list.

UltraScale represents a new breakthrough in Partial Reconfiguration technology, enabling reconfiguration of nearly all FPGA resource types, including I/O, Gigabit Transceivers, and clocking networks.

Professors and researchers associated with universities may receive licenses through the Xilinx University Program (XUP).  Learn more about access requirements and procedures for obtaining licenses here.


Default Default Title Date

Training Courses

Xilinx hands-on FPGA and Embedded Design training provides you the foundational knowledge necessary to begin designing right away. These programs target both engineers new to FPGA technology and experienced engineers developing complex connectivity, digital signal processing, or embedded solutions. Contact your local Sales Rep or Authorized Training Provider to see if your company has any Training Credits available. Learn more

Vivado QuickTake Video Tutorials

Xilinx is developing QuickTake Video Tutorials in order to assist our users in making the transition from the ISE software tools to the Vivado® Design Suite. This entire solution is brand new, so we can't rely on previous knowledge of the technology. Xilinx recognizes that not everyone has the time to read through the User Guide or perform software interactive tutorials. Learn more

Page Bookmarked