System Generator for DSP

System Generator for DSP™ is the industry’s leading architecture-level* design tool to define, test and implement high-performance DSP algorithms on Xilinx devices. Designed as an add-on toolbox for MathWorks Simulink®, System Generator for DSP takes advantage of pre-existing IP optimized for the FPGA fabric, which can be parameterized by the user to meet the quality and cost goals of the algorithms. System Generator for DSP features combined with the benefits of a rich simulation and verification environment offered by Simulink® enables the creation of production-quality DSP algorithms in a fraction of time compared to traditional RTL development times.

• New DSP Macro V1.0 that handles both DSP48 and DSP58
• Can now import Vitis HLS IP 

• 100+ RTL-optimized blocks within Simulink, many with C simulation models for 2-3X faster simulation vs RTL
• Integrate Xilinx IP, legacy RTL,  Simulink and MATLAB components of a DSP system
• Bit and cycle accurate floating and fixed-point simulations
• Hardware co-simulation to accelerate simulation and validate algorithm on hardware
• Automatic code generation from Simulink to packaged IP or low-level HDL
• Automatic generation of HDL test bench, including test vectors from simulation

• DSP modeling
  Build and debug high-performance DSP systems using Xilinx-optimized RTL IPs as blocks within Simulink for signal processing (e.g., FIR filters, FFTs) , error correction (e.g., Viterbi decoder, Reed-Solomon encoder/decoder), arithmetic, memories (e.g., FIFO, RAM, ROM), and digital logic. Enables access to DSP48 primitives within Simulink for high clock-rate designs.
  
  
• Bit and cycle accurate floating and fixed-point implementation
  System Generator supports bit and cycle accurate fixed-point and bit and cycle accurate single, double and custom precision floating-point.
  
  
• Automatic code generation of VHDL or Verilog or Packaged IP from Simulink
  Implement behavioral (RTL) generation and target specific Xilinx IP cores from the Xilinx Blockset. Package the design as an IP core that can be added to the Vivado IP catalog for use in another design, enabling design reuse and model sharing

• Hardware co-simulation
  A code generation option that enables validation and simulation acceleration by compiling designs into FPGA hardware that can be used in the loop with Simulink simulations validate working hardware and accelerate simulations in Simulink. System Generator supports Ethernet (10/100/Gigabit) and JTAG communication between a hardware platform and Simulink for supported boards and platforms

• Timing and Resource Analysis
  Verify timing closure and resource utilization of your designs (Post-synthesis or Post-Implementation) and correlate results with the System Generator model in Simulink through cross probing which accelerates the process of refining the design for performance or finding timing failures.

Comprehensive Device Support: Kintex®-7, Virtex®-7, Zynq®-7000, Artix®-7, Kintex UltraScale™, Kintex UltraScale+,Virtex UltraScale, Virtex UltraScale+, Zynq UltraScale+ RFSoC

Please refer to the Vivado Release Notes for release-specific information on parts and boards supported, compatible MATLAB versions and OS support