Architecture Wizards

Architecture wizards assist in configuring and implementing FPGA architectural block features. Unlike HDL templates, Wizards offer the designer the ability to customize hard and soft logic with step-by-step online guidance and help. In addition, wizards can create source code templates to be used as the basis for future design development, or for direct (non-GUI) design modification. For a comprehensive description of the FPGA architectural block functionality and operating modes, refer to the respective device-specific user guide for that block.

Wizards

• Clocking Wizard
• High-Speed Serial Transceiver Wizards
• SelectIO Interface Wizard
• XADC and System Monitor Wizards

Key Features

• Automated creation of HDL wrappers
• Instructional graphical user interface assistance
• Optimal hardened block attribute selection
• Power user support
• Example designs, testbenches, and scripts to run simulation and implementation

Delivery Mechanism and Requirements

Architecture Wizards are delivered through the Xilinx Vivado™ Design Suite and Xilinx CORE Generator™ tool’s. For more information refer to the respective Architecture Wizard's "Product Guides in the documentation links below. Refer to the Vivado / ISE® IP master release notes for information on supported SW and OS versions.

Clocking Wizard

The LogiCORE™ IP Clocking Wizard core creates HDL source code for a clock circuit customized to your clocking requirements. The wizard automatically selects an appropriate clocking primitive and provides the ability to configure buffering, feedback, and timing parameters for the clocking network. In addition, it interactively helps the user select the appropriate attributes for the selected primitive and override any wizard-calculated parameter. Besides generating source HDL for the clocking circuit, the wizard also provides a summary of the timing parameters calculated for the clock circuit as reported by the Xilinx timing analysis tools.

Additional Key Features

• Accepts up to two input clocks and up to seven output clocks per clock network
• Automatically chooses the correct clocking primitive for a selected device
• Automatically configures the clocking primitive based on user-selected clocking features
• Automatically calculates VCO frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements
• Automatically implements an overall configuration that supports phase shift and duty cycle requirements
• Provides the ability to override the selected clock primitive and any calculated attribute
• Provides spread spectrum clocking support
• Optionally buffers clock signals
• Provides timing estimates for the clock circuit as well as Xilinx Power Estimator (XPE) parameters