Architecture Wizards

Architecture wizards assist in the creation and implementation of FPGA architecture features. Wizards, unlike templates, offer the designer customization of hard and soft logic through a step-by-step online guidance and help. In addition, wizards create source code templates for future design development or direct (non-GUI) design modification. For a comprehensive description of block functionality and operating modes, refer to the respective device user guides:

Key Features

Automates the creation of HDL wrappers
Instructional graphical user interface assistance
Optimal harden block attributes selection
Power users support
Example design, testbench, implementation and simulation scripts

Delivery Mechanism and Requirements

Architecture wizards are delivered through the Xilinx CORE Generator™ tool’s architecture wizard section. For more information refer to the respective architecture wizards, "Getting Started Guide" found within the documentation links. Refer to the ISE® IP release notes in the documentation links for ISE version and OS support.

Clocking Wizard

The LogiCORE™ IP Clocking Wizard core creates HDL source code for a clock circuit customized for your clocking requirements. The wizard automatically selects an appropriate clocking primitive and allows for the configuration of buffering, feedback, and timing parameters for the clocking network. In addition, it interactively aids the selection of correct attributes for the selected primitive and allows overriding of any wizard-calculated parameter. As well as providing the clocking circuit as source HDL, the wizard delivers summary information about the timing parameters calculated for the clock circuit as reported by the Xilinx timing tools.

Additional Key Features

Accepts up to two input clocks and up to seven output clocks per clock network
Automatically chooses correct clocking primitive for a selected device
Automatically configures clocking primitive based on user-selected clocking features
Automatically calculates VCO frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements
Automatically implements overall configuration that supports phase shift and duty cycle requirements
Provides the ability to override the selected clock primitive and any calculated attribute
Optionally buffers clock signals
Provides timing estimates for the clock circuit and Xilinx Power Estimator (XPE) parameters

Clocking Wizards
Wizard	Device Family	Related Links	Documents
Clocking Wizard	Virtex®-6 HXT, LXT, SXT, -1L Spartan®-6 LX, LXT	Virtex-6 Spartan-6	Documents Release Notes Virtex-6 Datasheet Spartan-6 Datasheet

Cyclic Redundancy Check (CRC) Wizard

The LogiCORE IP CRC Wizard provides a LocalLink wrapper for the CRC hard macro. The CRC Wizard is used to customize the CRC block to meet a wide variety of requirements. In Virtex-5 devices, each GTP tile is paired with two CRC hard blocks. The CRC hard blocks can operate independently as two 32-bit input CRC modules (CRC32), or can be combined into a single 64-bit input CRC module (CRC64). The CRC modules use the standard 32-bit Ethernet polynomial for CRC calculation. The CRC hard blocks are independent of the transceiver blocks.

Additional Key Features

LocalLink wrapper for simple user interface
Supports CRC blocks on the Virtex-5 LXT/SXT/FXT devices
Uses CRC32 polynomial
Two 32-bit input CRC modules (CRC32) can be combined into a 64-bit input CRC module (CRC64)
Easy to use framing user interface
Support for variable REM feature on user LocalLink
Option to transpose/complement user data or CRC
ISIM simulation support

CRC Wizards
Wizard	Device Family	Related Links	Documents
CRC Wizard	Virtex-5 FXT, LXT, SXT	Virtex-5	Documents Release Notes Virtex-5 User Guide

High-Speed Serial Transceiver Wizard

The LogiCORE IP High-Speed Serial Transceiver Wizard automates the task of creating HDL wrappers to configure transceivers. The Wizard’s customization GUI allows you to configure one or more high-speed serial transceivers using pre-defined templates to support popular industry standards, or from scratch, to support a wide variety of custom protocols.

Sample of Protocols Templates

10 Gigabit Ethernet (XFI/SFI), 10G Base-R, Aurora, CPRI, Fibre Channel, Gigabit Ethernet (SGMII/1000Base-X), OBSAI, PCI Express® Gen1/2, Serial RapidIO and XAUI . Refer to the datasheet in the documentation link for a complete list of protocols.

Additional Key Features

Creates customized HDL wrappers to configure high-speed serial transceivers
Configures high-speed serial transceivers to conform to industry standard protocols using predefined templates directly, or tailor the templates for custom protocols
Automatically configures analog settings

High-Speed Serial Transceiver Wizards
Wizard	Device Family	Related Links	Documents
Virtex-6 FPGA GTH Transceiver Wizard	Virtex-6 HXT	Virtex-6	Documents Release Notes Virtex-6 Data Sheet
Virtex-6 FPGA GTX Transceiver Wizard	Virtex-6 HXT, LXT, -1L	Virtex-6	Documents Release Notes Virtex-6 Data Sheet
Virtex-5 RocketIO GTP Transceiver Wizard	Virtex-5 LXT, SXT	Virtex-5	Documents Release Notes Virtex-5 User Guide
Virtex-5 RocketIO GTX Transceiver Wizard	Virtex-5 FXT, TXT	Virtex-5	Documents Release Notes Virtex-5 User Guide
Virtex-4 RocketIO GT11 Transceiver Wizard	Virtex-4 FX	Virtex-4	Documents Release Notes Virtex-4 User Guide
Spartan-6 FPGA GTP Transceiver Wizard	Spartan-6 LXT	Spartan-6	Documents Release Notes Spartan-6 Data Sheet

SelectIO Interface Wizard

The LogiCORE IP SelectIO™ Interface Wizard assists the user in integrating IO logic into their system. It creates an HDL file (Verilog or VHDL) that creates IO logic such as IOSERDES and IODELAY blocks configured to customer requirements. Additionally, it instantiates and configures the desired IO clock primitive, connecting to the instantiated IO logic.

Additional Key Features

Supports input, output or directional busses
Simplifies the creation of clock circuitry to drive IO logic
Supports up to a 32-bit wide data bus
Supports optional data serialization of up to 8 bits
Supports optional data and/or clock delay insertion
supports single and double data rate data
Supports single-ended or differential standards for both clock and or data
Access to optional primitive ports
Can be used with PlanAhead™ for additional IO configuration

SelectIO Interface Wizards
Wizard	Device Family	Related Links	Documents
SelectIO Interface Wizard	Spartan-6 LX, LXT	Spartan-6	Documents Release Notes Spartan-6 Data Sheet

System Monitor Wizard

The LogiCORE IP System Monitor Wizard automates the task of instantiating System Monitor (SYSMON) in your HDL design. The Wizard's customization GUI allows you to easily configure System Monitor to your desired mode of operation.

Additional Key Features

Automatically calculates clock settings for correct operation
Simplifies channel sequencer initialization
Calculates user specified alarm limits

System Monitor Wizards
Wizard	Device Family	Related Links	Documents
System Monitor Wizard	Virtex-5 LX, LXT, SXT	Virtex-5	Documents Release Notes Virtex-5 User Guide