Architecture Wizards

Architecture wizards assist in configuring and implementing FPGA architectural block features. Unlike HDL templates, Wizards offer the designer the ability to customize hard and soft logic with step-by-step online guidance and help. In addition, wizards can create source code templates to be used as the basis for future design development, or for direct (non-GUI) design modification. For a comprehensive description of the FPGA architectural block functionality and operating modes, refer to the respective device-specific user guide for that block.

Wizards
Key Features
  • Automated creation of HDL wrappers
  • Instructional graphical user interface assistance
  • Optimal hardened block attribute selection
  • Power user support
  • Example designs, testbenches, and scripts to run simulation and implementation
Delivery Mechanism and Requirements

Architecture Wizards are delivered through the Xilinx Vivado™ Design Suite and Xilinx CORE Generator™ tool’s. For more information refer to the respective Architecture Wizard's "Product Guides in the documentation links below. Refer to the Vivado / ISE® IP master release notes for information on supported SW and OS versions.

Clocking Wizard

The LogiCORE™ IP Clocking Wizard core creates HDL source code for a clock circuit customized to your clocking requirements. The wizard automatically selects an appropriate clocking primitive and provides the ability to configure buffering, feedback, and timing parameters for the clocking network. In addition, it interactively helps the user select the appropriate attributes for the selected primitive and override any wizard-calculated parameter. Besides generating source HDL for the clocking circuit, the wizard also provides a summary of the timing parameters calculated for the clock circuit as reported by the Xilinx timing analysis tools.

Additional Key Features

  • Accepts up to two input clocks and up to seven output clocks per clock network
  • Automatically chooses the correct clocking primitive for a selected device
  • Automatically configures the clocking primitive based on user-selected clocking features
  • Automatically calculates VCO frequency for primitives with an oscillator, and provides multiply and divide values based on input and output frequency requirements
  • Automatically implements an overall configuration that supports phase shift and duty cycle requirements
  • Provides the ability to override the selected clock primitive and any calculated attribute
  • Provides spread spectrum clocking support
  • Optionally buffers clock signals
  • Provides timing estimates for the clock circuit as well as Xilinx Power Estimator (XPE) parameters
Clocking Wizards
Wizard Device Family Related Links Documents
Clocking Wizard Kintex® UltraScale™
Virtex® UltraScale
Artix®-7
Kintex-7
Virtex-7
Zynq™-7000 AP SoC
Virtex-6 CXT, HXT, LXT, SXT
Virtex-6 Lower Power
Spartan®-6 LX, LXT
Kintex UltraScale
Virtex UltraScale
Kintex-7
Artix-7
Virtex-7
Zynq-7000
Virtex-6
Spartan-6

Documents
Release Notes
Virtex-7 Data Sheet
7 Series Data Sheet
Virtex-6 Data Sheet
Spartan-6 Data Sheet
High-Speed Serial Transceiver Wizards

LogiCORE IP High-Speed Serial Transceiver Wizards automate the task of creating HDL wrappers to configure Xilinx FPGA on-chip transceivers. Each Wizard’s customization GUI allows users to configure one or more high-speed serial transceivers using either pre-defined templates supporting popular industry standards, or from scratch, to support a wide variety of custom protocols.

Sample Protocol Templates Supported

10 Gigabit Ethernet (XFI/SFI), 10GBASE-R, Aurora, CPRI, Fibre Channel, Gigabit Ethernet (SGMII/1000BASE-X),HD-SDI, OBSAI, PCI Express® Gen1/2, Serial RapidIO, SATA, DisplayPort, and XAUI. Refer to the appropriate Wizard user guide in the documentation links below for a complete list of protocols supported by the Wizard.

The Right FPGA Gigabit Transceiver Makes All the Difference

Additional Key Features

  • Creates customized HDL wrappers to configure high-speed serial transceivers
  • Configures high-speed serial transceivers to conform to industry standard protocols using predefined templates directly, and also allows the user to tailor the templates for custom protocols
  • Automatically configures analog settings
  • GUI option to include or exclude shareable logic resources
  • Optional ports to enable transceiver core debug
High-Speed Serial Transceiver Wizards
Wizard Device Family Related Links Documents
7 Series FPGA Transceiver Wizard Virtex-7
Kintex-7
Artix-7
Zynq-7000 AP SoC
Virtex-7
Kintex-7
Artix-7
Zynq-7000
Documents
Release Notes
7 Series FPGAs Data Sheets
Zynq-7000 Data Sheets

Virtex-6 FPGA GTH Transceiver Wizard Virtex-6 HXT Virtex-6 Documents
Release Notes
Virtex-6 Data Sheet
Virtex-6 FPGA GTX Transceiver Wizard Virtex-6 CXT, HXT, LXT, SXT
Virtex-6 Lower Power
Virtex-6 Documents
Release Notes
Virtex-6 Data Sheet
Virtex-5  FPGA RocketIO GTP Transceiver Wizard Virtex-5 LXT, SXT
Virtex-5 Documents
Release Notes
Virtex-5 Data Sheet
Virtex-5  FPGA RocketIO GTX Transceiver Wizard Virtex-5 FXT, TXT
Virtex-5 Documents
Release Notes
Virtex-5 Data Sheet
Virtex-4 FX FPGA RocketIO Multi-Gigabit Transceiver Wizard Virtex-4 FX Virtex-4 Documents
Release Notes
Virtex-4 FX Data Sheet
Spartan-6 FPGA GTP Transceiver Wizard Spartan-6 LXT
Spartan-6 Documents
Release Notes
Spartan-6 Data Sheet
SelectIO Interface Wizard

The LogiCORE IP SelectIO™ Interface Wizard assists the user in integrating IO logic into their system. It creates an HDL file (Verilog or VHDL) that creates IO logic such as IOSERDES and IODELAY blocks configured to customer requirements. Additionally, it instantiates and configures the desired IO clock primitive, connecting to the instantiated IO logic.

Additional Key Features

  • Supports input, output or directional busses
  • Simplifies the creation of clock circuitry to drive IO logic
  • Supports up to a 32-bit wide data bus
  • Supports optional data serialization of up to 8 bits
  • Supports optional data and/or clock delay insertion
  • supports single and double data rate data
  • Supports single-ended or differential standards for both clock and or data
  • Access to optional primitive ports
  • Can be used with PlanAhead™ for additional IO configuration
  • Implements an optional Phase detector functionality
SelectIO Interface Wizards
Wizard Device Family Related Links Documents
SelectIO Interface Wizard Artix-7
Kintex-7
Virtex-7
Zynq-7000 AP SoC
Virtex-6 CXT, HXT, LXT, SXT -1L
Spartan-6Q, -1L
Virtex-7
Kintex-7
Artix-7
Zynq-7000
Virtex-6
Spartan-6
Documents
Release Notes
7 Series FPGAs Data Sheets
Virtex-6 Data Sheet
Spartan-6 Data Sheet
XADC and System Monitor (SYSMON) Wizards

The LogiCORE IP XADC Wizard for 7 Series FPGAs automates the task of instantiating the XADC block in your HDL design. The counterpart of the XADC block in 7 Series FPGAs in UltraScale, Virtex-6 and Virtex-5 FPGAs is the System Monitor block, which can be configured using the LogiCORE IP System Management Wizard for UltraScale Devices and with the LogiCORE IP System Monitor Wizard for Virtex-6 and Virtex-5 FPGAs. The customization GUIs of both wizards make it easy for the user to configure these hardware blocks to the desired mode of operation.

Additional Key Features

  • Automatically calculates clock settings for correct operation
  • Simplifies channel sequencer initialization
  • Calculates user specified alarm limits
  • Optional AXI4 Lite interface
  • Optional AXI4-Stream Interface
XADC and System Monitor Wizards
Wizard Device Family Related Links Documents
XADC Wizard Artix-7
Kintex-7
Virtex-7
Zynq-7000
Virtex-7
Kintex-7
Artix-7
Zynq-7000

Documents
Release Notes
7 Series FPGAs Data Sheet
System Management Wizard UltraSale UltraScale Documents
System Monitor Wizard Virtex-6 LXT, SXT, HXT
Virtex-6 Lower Power
Virtex-5 LX, LXT, SXT, TXT, FXT
Virtex-6
Virtex-5
Documents
Release Notes
Virtex-6 Data Sheet
Virtex-5 Data Sheet
 
UltraScale FPGA Transceivers Wizard

The LogiCORE IP UltraScale FPGAs Transceivers Wizard generates customized HDL to configure the UltraScale FPGA on-chip serial transceivers. The wizard’s customization GUI allows users to configure one or more high-speed serial transceivers using either pre-defined protocol presets supporting popular industry standards, or start from scratch, to support a wide variety of custom protocols.

Additional Key Features

  • Creates customized protocol presets to configure high-speed serial transceivers in UltraScale FPGAs
  • Protocol presets provided for Aurora 8B/10B, Aurora 64B/66B, CEI-11G, CPRI™, JESD204B, Interlaken, 10GBASE-R, 10GBASE-KR, Gigabit Ethernet, XAUI, RXAUI, XLAUI, CAUI, QSGMII, 3G-SDI, HD-SDI and OTL 4.10
UltraScale FPGA Transceivers Wizard
Wizard Device Family Related Links Documents
UltraScale FPGA Transceivers Wizard UltraScale® UltraScale Documents
UltraScale Data Sheets
 
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